 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| revision date: aug 04, 2006 8 h8/3827r group , h8/3827s group , h8/38327 group, h8/38427 group hardware manual renesas 8-bit single-chip microcomputer h8 family/h8/300l super low power series rev. 6.00 rej09b0144-0600 h8/3827r group h8/3822r h8/3823r h8/3824r h8/3825r h8/3826r h8/3827r h8/3827s group h8/3824s h8/3825s h8/3826s h8/3827s h8/38327 group h8/38322 h8/38323 h8/38324 h8/38325 h8/38326 h8/38327 h8/38427 group h8/38422 h8/38423 h8/38424 h8/38425 h8/38426 h8/38427
rev. 6.00 aug 04, 2006 page ii of xxxiv 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials rev. 6.00 aug 04, 2006 page iii of xxxiv preface the h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group are high- performance single-chip microcomputers that integrate peripheral functions necessary for system configuration with an h8/300l cpu core. the on-chip peripheral functions include rom, ram, six timers, 14-bit pwm, a serial communication interface (sci), an a/d converter, lcd controller/driver, and i/o ports, providing an ideal configuration as a microcomputer for embedding in sophisticated control systems. prom (ztat? * 1 ), flash memory (f-ztat? * 2 ), and mask rom are available as on-chip rom, enabling users to respond quickly and flexibly to changing application specifications and the demands of the transition from initial to full-fledged volume production. notes: 1. ztat is a trademark of renesas technology corp. 2. f-ztat is a trademark of renesas technology corp. intended readership: this manual is intended for users undertaking the design of an application system using the h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group. readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers. purpose: the purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group. details of execution instructions can be found in the h8/300l series programming manual, which should be read in conjunction with the present manual. using this manual: ? for an overall understanding of the h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group's functions follow the table of contents. this manual is broadly divided into sections on the cpu, system control functions, peripheral functions, and electrical characteristics. ? for a detailed understanding of cpu functions refer to the separate publication h8/300l series programming manual. note on bit notation: bits are shown in high-to-low order from left to right. rev. 6.00 aug 04, 2006 page iv of xxxiv notes: the following limitations apply when using the on-chip emulator for program development and debugging. 1. pin p3 2 is reserved for use exclusively by the on-chip emulator and cannot be used for other operations. 2. pins p8 5 , p8 6 , and p8 7 cannot be used. in order to use these pins it is necessary to install additional hardware on the user board. 3. the address area from h'e000 to h'efff is used by the on-chip emulator and therefore cannot be accessed by the user. 4. the address area from h'f300 to h'f6ff must not be accessed under any circumstances. 5. when the on-chip emulator is used, pin p3 2 functions as an i/o pin, pins p8 5 and p8 6 function as input pins, and pin p8 7 functions as an output pin. 6. it is necessary to change the user board for lcd display debugging. this item does not apply if lcd display is not used or if the emulator is not operated in writer mode. user board changes the following changes are necessary. ? connect pin v1 to the v cc power supply. also connect capacitors and resistors to pins v1, v2, and v3. connect a capacitor and a resistor to pins v1, v2, and v3. ? no seg signals are output from pins p8 5 /seg30, p8 6 /seg31, and p8 7 /seg32, so the display is unstable. in addition, a dc voltage is applied. if damage to the lcd is a concern, disconnect the above three pins from the lcd. a connection example is shown below. refer to the emulator user?s manual for information on other settings. normal operation debugging vcc lcd h8/38327 h8/38427 vcc lcd h8/38327 h8/38427 p8 7 /seg32 p8 6 /seg31 p8 5 /seg30 p8 7 /seg32 p8 6 /seg31 p8 5 /seg30 v2 v3 r = 240 ? * c = 0.1 * r r r c c c v0 vcc v1 v0 vcc v2 v3 connect connect dis- connect disonnect disconnect connect emulator connectors emulator connectors note: * r and c values are intended only as guidelines. they may be adjusted based on the indications. rev. 6.00 aug 04, 2006 page v of xxxiv 7. during a break, the watchdog timer continues to operate. therefore, an internal reset is generated if an overflow occurs during the break. related material: the latest information is available at our web site. please make sure that you have the most up-to-date information available. (http://www.renesas.com/) user's manuals on this lsi: manual title document no. h8/3827r group, h8/3827s group, h8/38327 group, h8/38427 group hardware manual this manual h8/300l series programming manual rej09b0214-0200 user's manuals for development tools: manual title document no. c/c++ compiler, assembler, optimizing linkage editor user?s manual rej10b0161-0100 h8s, h8/300 series simulator/debugger user?s manual rej10b0211-0200 high-performance embedded workshop user?s manual ade-702-201 h8s, h8/300 series high-performance embedded workshop, high-performance debugging interface user?s manual ade-702-231 application note: manual title document no. h8/300l series application note ade-502-065 rev. 6.00 aug 04, 2006 page vi of xxxiv rev. 6.00 aug 04, 2006 page vii of xxxiv main revisions for this edition item page revision (see manual for details) all ? ?under development? indication deleted from h8/38427 group preface iv note 6. (user board changes) amended, and note 7. added 6. it is necessary to change the user board for lcd display debugging. this item does not apply if lcd display is not used or if the emulator is not operated in writer mode. user board changes the following changes are necessary. ? connect pin v1 to the v cc power supply. also connect capacitors and resistors to pins v1, v2, and v3. connect a capacitor and a resistor to pins v1, v2, and v3. normal operation debugging vcc lcd h8/38327 h8/38427 vcc lcd h8/38327 h8/38427 p8 7 /seg32 p8 6 /seg31 p8 5 /seg30 p8 7 /seg32 p8 6 /seg31 p8 5 /seg30 v2 v3 r = 240 ? * c = 0.1 * r r r c c c v0 vcc v1 v0 vcc v2 v3 connect connect dis- connect disonnect disconnect connect emulator connectors emulator connectors note: * r and c values are intended only as guidelines. they may be adjusted based on the indications. 7. during a break, the watchdog timer continues to operate. therefore, an internal reset is generated if an overflow occurs during the break. 1.3.2 pin functions table 1.6 pin functions 28 table amended pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions system control test 8 10 input test pin: this pin is reserved and cannot be used. it should be connected to v ss . 8.3.1 overview 203 description amended port 3 is a 8-bit i/o port, configured as shown in figure 8.2. in the f-ztat version, the on-chip pull-up mos for pin p3 2 is on during the reset period. it turns off and normal operation resumes after the reset is cleared. this should be considered when making connections to external circuitry. note that in the mask rom and ztat versions p3 2 continues to operate normally. rev. 6.00 aug 04, 2006 page viii of xxxiv item page revision (see manual for details) 8.3.4 pin states table 8.7 port 3 pin states 211 table and notes amended pins reset sleep subsleep standby watch subactive active p3 7 /aevl p3 6 /aevh p3 5 /txd 31 p3 4 /rxd 31 p3 3 /sck 31 high- impedance retains previous state retains previous state high- impedance * 1 retains previous state functional functional p3 2 / reso * 2 reso output p3 2 * 4 pull-up mos on p3 2 * 3 p3 1 /ud * 2 p3 1 /ud/excl * 3 * 4 p3 0 /pwm high- impedance notes: 1. a high-level signal is output when the mos pull-up is in the on state. 2. applies to h8/3827r group and h8/3827s group. 3. applies to the mask rom version of the h8/38327 group and h8/38427 group. 4. applies to the f-ztat version of the h8/38327 group and h8/38427 group. 8.12.1 the management of the un-use terminal 236 description amended ? if an unused pin is an output pin, handle it in one of the following ways: ? set the output of the unused pin to high and pull it up to v cc with an external resistor of approximately 100 k ? . ? set the output of the unused pin to low and pull it down to vss with an external resistor of approximately 100 k ? . c.2 block diagrams of port 3 figure c.2 (e-2) port 3 block diagram (pin p3 2 in the mask rom version of the h8/38327 group and h8/38427 group) 593 figure title amended figure c.2 (e-3) port 3 block diagram (pin p3 2 in the f-ztat version of the h8/38327 group and h8/38427 group) 594 newly added rev. 6.00 aug 04, 2006 page ix of xxxiv item page revision (see manual for details) appendix d port states in the different processing states table d.1 port states overview 608 notes amended notes: 1. high level output when mos pull-up is in on state. 2. reset output from p3 2 pin only (h8/3827r group and h8/3827s group). on-chip pull-up mos turns on for pin p3 2 only (f- ztat version of the h8/38327 group and h8/38427 group). rev. 6.00 aug 04, 2006 page x of xxxiv rev. 6.00 aug 04, 2006 page xi of xxxiv contents section 1 overview ............................................................................................................. 1 1.1 overview.................................................................................................................... ....... 1 1.2 internal block diagram..................................................................................................... 6 1.3 pin arrangement and functions........................................................................................ 8 1.3.1 pin arrangement .................................................................................................. 8 1.3.2 pin functions ....................................................................................................... 27 section 2 cpu ...................................................................................................................... 33 2.1 overview.................................................................................................................... ....... 33 2.1.1 features................................................................................................................ 33 2.1.2 address space...................................................................................................... 34 2.1.3 register configuration......................................................................................... 34 2.2 register descriptions ....................................................................................................... .35 2.2.1 general registers ................................................................................................. 35 2.2.2 control registers ................................................................................................. 35 2.2.3 initial register values.......................................................................................... 37 2.3 data formats ................................................................................................................ ..... 37 2.3.1 data formats in general registers ...................................................................... 38 2.3.2 memory data formats ......................................................................................... 39 2.4 addressing modes............................................................................................................ .40 2.4.1 addressing modes ............................................................................................... 40 2.4.2 effective address calculation.............................................................................. 42 2.5 instruction set ............................................................................................................. ...... 46 2.5.1 data transfer instructions.................................................................................... 48 2.5.2 arithmetic operations.......................................................................................... 50 2.5.3 logic operations.................................................................................................. 51 2.5.4 shift operations ................................................................................................... 52 2.5.5 bit manipulations................................................................................................. 54 2.5.6 branching instructions ......................................................................................... 58 2.5.7 system control instructions................................................................................. 60 2.5.8 block data transfer instruction........................................................................... 62 2.6 basic operational timing ................................................................................................. 63 2.6.1 access to on-chip memory (ram, rom)......................................................... 63 2.6.2 access to on-chip peripheral modules............................................................... 64 2.7 cpu states .................................................................................................................. ...... 65 2.7.1 overview.............................................................................................................. 65 2.7.2 program execution state...................................................................................... 67 rev. 6.00 aug 04, 2006 page xii of xxxiv 2.7.3 program halt state............................................................................................... 67 2.7.4 exception-handling state .................................................................................... 67 2.8 memory map .................................................................................................................. .. 68 2.8.1 memory map ....................................................................................................... 68 2.9 application notes ........................................................................................................... .. 74 2.9.1 notes on data access .......................................................................................... 74 2.9.2 notes on bit manipulation................................................................................... 76 2.9.3 notes on use of the eepmov instruction .......................................................... 82 section 3 exception handling ......................................................................................... 83 3.1 overview.................................................................................................................... ....... 83 3.2 reset....................................................................................................................... ........... 83 3.2.1 overview.............................................................................................................. 83 3.2.2 reset sequence .................................................................................................... 83 3.2.3 interrupt immediately after reset ........................................................................ 84 3.3 interrupts .................................................................................................................. ......... 85 3.3.1 overview.............................................................................................................. 85 3.3.2 interrupt control registers................................................................................... 87 3.3.3 external interrupts ............................................................................................... 97 3.3.4 internal interrupts................................................................................................. 98 3.3.5 interrupt operations ............................................................................................. 99 3.3.6 interrupt response time...................................................................................... 104 3.4 application notes ........................................................................................................... .. 105 3.4.1 notes on stack area use ..................................................................................... 105 3.4.2 notes on rewriting port mode registers............................................................. 106 3.4.3 method for clearing interrupt request flags ...................................................... 108 section 4 clock pulse generators ................................................................................... 109 4.1 overview.................................................................................................................... ....... 109 4.1.1 block diagram..................................................................................................... 109 4.1.2 system clock and subclock................................................................................. 109 4.2 system clock generator ................................................................................................... 110 4.3 subclock generator.......................................................................................................... . 112 4.4 prescalers .................................................................................................................. ........ 115 4.5 note on oscillators......................................................................................................... ... 116 4.5.1 definition of oscillation stabilization wait time ............................................... 117 4.5.2 notes on use of crystal oscillator element (excluding ceramic oscillator element)............................................................................................................... 119 rev. 6.00 aug 04, 2006 page xiii of xxxiv section 5 power-down modes ........................................................................................ 121 5.1 overview.................................................................................................................... ....... 121 5.1.1 system control registers..................................................................................... 124 5.2 sleep mode .................................................................................................................. ..... 128 5.2.1 transition to sleep mode..................................................................................... 128 5.2.2 clearing sleep mode............................................................................................ 129 5.2.3 clock frequency in sleep (medium-speed) mode.............................................. 129 5.3 standby mode ................................................................................................................ ... 129 5.3.1 transition to standby mode................................................................................. 129 5.3.2 clearing standby mode ....................................................................................... 130 5.3.3 oscillator settling time after standby mode is cleared ..................................... 131 5.3.4 standby mode transition and pin states ............................................................. 131 5.3.5 notes on external input signal changes before/after standby mode.................. 132 5.4 watch mode.................................................................................................................. .... 134 5.4.1 transition to watch mode ................................................................................... 134 5.4.2 clearing watch mode .......................................................................................... 134 5.4.3 oscillator settling time after watch mode is cleared ........................................ 134 5.4.4 notes on external input signal changes before/after watch mode .................... 135 5.5 subsleep mode............................................................................................................... ... 135 5.5.1 transition to subsleep mode ............................................................................... 135 5.5.2 clearing subsleep mode ...................................................................................... 135 5.6 subactive mode .............................................................................................................. .. 136 5.6.1 transition to subactive mode .............................................................................. 136 5.6.2 clearing subactive mode..................................................................................... 136 5.6.3 operating frequency in subactive mode............................................................. 136 5.7 active (medium-speed) mode ......................................................................................... 137 5.7.1 transition to active (medium-speed) mode ....................................................... 137 5.7.2 clearing active (medium-speed) mode.............................................................. 137 5.7.3 operating frequency in active (medium-speed) mode...................................... 137 5.8 direct transfer ............................................................................................................. ..... 138 5.8.1 overview of direct transfer ................................................................................ 138 5.8.2 direct transition times ....................................................................................... 139 5.8.3 notes on external input signal changes before/after direct transition.............. 141 5.9 module standby mode...................................................................................................... 142 5.9.1 setting module standby mode ............................................................................ 142 5.9.2 clearing module standby mode .......................................................................... 142 5.9.3 usage note........................................................................................................... 144 section 6 rom ..................................................................................................................... 145 6.1 overview.................................................................................................................... ....... 145 rev. 6.00 aug 04, 2006 page xiv of xxxiv 6.1.1 block diagram..................................................................................................... 145 6.2 h8/3827r prom mode ................................................................................................... 146 6.2.1 setting to prom mode ....................................................................................... 146 6.2.2 socket adapter pin arrangement and memory map........................................... 146 6.3 h8/3827r programming ................................................................................................... 149 6.3.1 writing and verifying.......................................................................................... 149 6.3.2 programming precautions .................................................................................... 154 6.4 reliability of programmed data ....................................................................................... 155 6.5 flash memory overview................................................................................................... 156 6.5.1 features................................................................................................................ 15 6 6.5.2 block diagram..................................................................................................... 157 6.5.3 block configuration............................................................................................. 157 6.5.4 register configuration......................................................................................... 159 6.6 descriptions of registers of the flash memory................................................................ 160 6.6.1 flash memory control register 1 (flmcr1)..................................................... 160 6.6.2 flash memory control register 2 (flmcr2)..................................................... 162 6.6.3 erase block register (ebr) ................................................................................ 163 6.6.4 flash memory power control register (flpwcr) ............................................ 164 6.6.5 flash memory enable register (fenr) .............................................................. 165 6.7 on-board programming modes ........................................................................................ 166 6.7.1 boot mode ........................................................................................................... 166 6.7.2 programming/erasing in user program mode..................................................... 169 6.8 flash memory programming/erasing ............................................................................... 169 6.8.1 program/program-verify ..................................................................................... 170 6.8.2 erase/erase-verify............................................................................................... 173 6.8.3 interrupt handling when programming/erasing flash memory.......................... 173 6.9 program/erase protection.................................................................................................. 17 5 6.9.1 hardware protection ............................................................................................ 175 6.9.2 software protection.............................................................................................. 175 6.9.3 error protection.................................................................................................... 175 6.10 programmer mode ............................................................................................................ 176 6.10.1 socket adapter..................................................................................................... 176 6.10.2 programmer mode commands ............................................................................ 176 6.10.3 memory read mode ............................................................................................ 179 6.10.4 auto-program mode ............................................................................................ 182 6.10.5 auto-erase mode ................................................................................................. 184 6.10.6 status read mode ................................................................................................ 185 6.10.7 status polling ....................................................................................................... 187 6.10.8 programmer mode transition time..................................................................... 188 6.10.9 notes on memory programming.......................................................................... 188 rev. 6.00 aug 04, 2006 page xv of xxxiv 6.11 power-down states for flash memory............................................................................. 189 section 7 ram ..................................................................................................................... 191 7.1 overview.................................................................................................................... ....... 191 7.1.1 block diagram..................................................................................................... 191 section 8 i/o ports .............................................................................................................. 193 8.1 overview.................................................................................................................... ....... 193 8.2 port 1...................................................................................................................... ........... 195 8.2.1 overview.............................................................................................................. 195 8.2.2 register configuration and description............................................................... 195 8.2.3 pin functions ....................................................................................................... 200 8.2.4 pin states.............................................................................................................. 20 2 8.2.5 mos input pull-up.............................................................................................. 202 8.3 port 3...................................................................................................................... ........... 203 8.3.1 overview.............................................................................................................. 203 8.3.2 register configuration and description............................................................... 203 8.3.3 pin functions ....................................................................................................... 209 8.3.4 pin states.............................................................................................................. 21 1 8.3.5 mos input pull-up.............................................................................................. 211 8.4 port 4...................................................................................................................... ........... 212 8.4.1 overview.............................................................................................................. 212 8.4.2 register configuration and description............................................................... 212 8.4.3 pin functions ....................................................................................................... 214 8.4.4 pin states.............................................................................................................. 21 5 8.5 port 5...................................................................................................................... ........... 215 8.5.1 overview.............................................................................................................. 215 8.5.2 register configuration and description............................................................... 216 8.5.3 pin functions ....................................................................................................... 218 8.5.4 pin states.............................................................................................................. 21 8 8.5.5 mos input pull-up.............................................................................................. 219 8.6 port 6...................................................................................................................... ........... 219 8.6.1 overview.............................................................................................................. 219 8.6.2 register configuration and description............................................................... 220 8.6.3 pin functions ....................................................................................................... 221 8.6.4 pin states.............................................................................................................. 22 2 8.6.5 mos input pull-up.............................................................................................. 222 8.7 port 7...................................................................................................................... ........... 223 8.7.1 overview.............................................................................................................. 223 8.7.2 register configuration and description............................................................... 223 rev. 6.00 aug 04, 2006 page xvi of xxxiv 8.7.3 pin functions ....................................................................................................... 225 8.7.4 pin states.............................................................................................................. 22 5 8.8 port 8...................................................................................................................... ........... 226 8.8.1 overview.............................................................................................................. 226 8.8.2 register configuration and description............................................................... 226 8.8.3 pin functions ....................................................................................................... 228 8.8.4 pin states.............................................................................................................. 22 9 8.9 port a...................................................................................................................... .......... 229 8.9.1 overview.............................................................................................................. 229 8.9.2 register configuration and description............................................................... 230 8.9.3 pin functions ....................................................................................................... 231 8.9.4 pin states.............................................................................................................. 23 2 8.10 port b ..................................................................................................................... ........... 232 8.10.1 overview.............................................................................................................. 232 8.10.2 register configuration and description............................................................... 233 8.11 input/output data inversion function .............................................................................. 233 8.11.1 overview.............................................................................................................. 233 8.11.2 register configuration and descriptions ............................................................. 234 8.11.3 note on modification of serial port control register ......................................... 236 8.12 application note ........................................................................................................... .... 236 8.12.1 the management of the un-use terminal .......................................................... 236 section 9 timers .................................................................................................................. 237 9.1 overview.................................................................................................................... ....... 237 9.2 timer a..................................................................................................................... ........ 238 9.2.1 overview.............................................................................................................. 238 9.2.2 register descriptions ........................................................................................... 240 9.2.3 timer operation................................................................................................... 245 9.2.4 timer a operation states .................................................................................... 246 9.2.5 application note.................................................................................................. 246 9.3 timer c ..................................................................................................................... ........ 247 9.3.1 overview.............................................................................................................. 247 9.3.2 register descriptions ........................................................................................... 249 9.3.3 timer operation................................................................................................... 252 9.3.4 timer c operation states..................................................................................... 254 9.3.5 usage note........................................................................................................... 255 9.4 timer f..................................................................................................................... ......... 256 9.4.1 overview.............................................................................................................. 256 9.4.2 register descriptions ........................................................................................... 259 9.4.3 cpu interface....................................................................................................... 266 rev. 6.00 aug 04, 2006 page xvii of xxxiv 9.4.4 operation ............................................................................................................. 269 9.4.5 application notes ................................................................................................ 272 9.5 timer g..................................................................................................................... ........ 276 9.5.1 overview.............................................................................................................. 276 9.5.2 register descriptions ........................................................................................... 279 9.5.3 noise canceler ..................................................................................................... 284 9.5.4 operation ............................................................................................................. 286 9.5.5 application notes ................................................................................................ 291 9.5.6 timer g application example ............................................................................. 295 9.6 watchdog timer .............................................................................................................. . 296 9.6.1 overview.............................................................................................................. 296 9.6.2 register descriptions ........................................................................................... 297 9.6.3 timer operation................................................................................................... 301 9.6.4 watchdog timer operation states ....................................................................... 302 9.7 asynchronous event counter (aec)................................................................................ 303 9.7.1 overview.............................................................................................................. 303 9.7.2 register descriptions ........................................................................................... 305 9.7.3 operation ............................................................................................................. 310 9.7.4 asynchronous event counter operation modes.................................................. 311 9.7.5 application notes ................................................................................................ 312 section 10 serial communication interface ................................................................ 315 10.1 overview................................................................................................................... ........ 315 10.1.1 features................................................................................................................ 3 15 10.1.2 block diagram..................................................................................................... 317 10.1.3 pin configuration................................................................................................. 318 10.1.4 register configuration......................................................................................... 318 10.2 register descriptions ...................................................................................................... .. 319 10.2.1 receive shift register (rsr) .............................................................................. 319 10.2.2 receive data register (rdr) .............................................................................. 319 10.2.3 transmit shift register (tsr) ............................................................................. 320 10.2.4 transmit data register (tdr)............................................................................. 320 10.2.5 serial mode register (smr)................................................................................ 321 10.2.6 serial control register 3 (scr3)......................................................................... 324 10.2.7 serial status register (ssr) ................................................................................ 328 10.2.8 bit rate register (brr) ...................................................................................... 332 10.2.9 clock stop register 1 (ckstpr1)...................................................................... 337 10.2.10 serial port control register (spcr).................................................................... 338 10.3 operation.................................................................................................................. ......... 340 10.3.1 overview.............................................................................................................. 340 rev. 6.00 aug 04, 2006 page xviii of xxxiv 10.3.2 operation in asynchronous mode ....................................................................... 345 10.3.3 operation in synchronous mode ......................................................................... 354 10.3.4 multiprocessor communication function............................................................ 361 10.4 interrupts ................................................................................................................. .......... 368 10.5 application notes .......................................................................................................... ... 369 section 11 14-bit pwm ..................................................................................................... 375 11.1 overview................................................................................................................... ........ 375 11.1.1 features................................................................................................................ 3 75 11.1.2 block diagram..................................................................................................... 376 11.1.3 pin configuration................................................................................................. 376 11.1.4 register configuration......................................................................................... 377 11.2 register descriptions ...................................................................................................... .. 377 11.2.1 pwm control register (pwcr).......................................................................... 377 11.2.2 pwm data registers u and l (pwdru, pwdrl)............................................ 378 11.2.3 clock stop register 2 (ckstpr2)...................................................................... 379 11.3 operation.................................................................................................................. ......... 380 11.3.1 operation ............................................................................................................. 380 11.3.2 pwm operation modes ....................................................................................... 381 section 12 a/d converter ................................................................................................. 383 12.1 overview................................................................................................................... ........ 383 12.1.1 features................................................................................................................ 3 83 12.1.2 block diagram..................................................................................................... 384 12.1.3 pin configuration................................................................................................. 385 12.1.4 register configuration......................................................................................... 385 12.2 register descriptions ...................................................................................................... .. 386 12.2.1 a/d result registers (adrrh, adrrl)........................................................... 386 12.2.2 a/d mode register (amr) ................................................................................. 386 12.2.3 a/d start register (adsr).................................................................................. 388 12.2.4 clock stop register 1 (ckstpr1)...................................................................... 389 12.3 operation.................................................................................................................. ......... 390 12.3.1 a/d conversion operation .................................................................................. 390 12.3.2 start of a/d conversion by external trigger input............................................. 390 12.3.3 a/d converter operation modes ......................................................................... 391 12.4 interrupts ................................................................................................................. .......... 391 12.5 typical use ................................................................................................................ ....... 392 12.6 application notes .......................................................................................................... ... 396 12.6.1 application notes ................................................................................................ 396 12.6.2 permissible signal source impedance ................................................................. 396 rev. 6.00 aug 04, 2006 page xix of xxxiv 12.6.3 influences on absolute precision......................................................................... 397 section 13 lcd controller/driver ................................................................................. 399 13.1 overview................................................................................................................... ........ 399 13.1.1 features................................................................................................................ 3 99 13.1.2 block diagram..................................................................................................... 400 13.1.3 pin configuration................................................................................................. 401 13.1.4 register configuration......................................................................................... 401 13.2 register descriptions ...................................................................................................... .. 402 13.2.1 lcd port control register (lpcr)..................................................................... 402 13.2.2 lcd control register (lcr)............................................................................... 404 13.2.3 lcd control register 2 (lcr2).......................................................................... 406 13.2.4 clock stop register 2 (ckstpr2)...................................................................... 408 13.3 operation.................................................................................................................. ......... 409 13.3.1 settings up to lcd display ................................................................................ 409 13.3.2 relationship between lcd ram and display .................................................... 412 13.3.3 luminance adjustment function (v 0 pin)........................................................... 419 13.3.4 low-power-consumption lcd drive system .................................................... 420 13.3.5 operation in power-down modes ....................................................................... 424 13.3.6 boosting the lcd drive power supply............................................................... 425 13.3.7 connection to hd66100 ...................................................................................... 426 section 14 power supply circuit .................................................................................... 429 14.1 overview................................................................................................................... ........ 429 14.2 when using internal power supply step-down circuit................................................... 429 14.3 when not using internal power supply step-down circuit............................................ 430 14.4 h8/3827s group ............................................................................................................. .. 430 14.5 notes on switching from the h8/3827r to the h8/38327 or h8/38427 ........................... 430 section 15 electrical characteristics .............................................................................. 431 15.1 h8/3827r group absolute maximum ratings (regular specifications) ......................... 431 15.2 h8/3827r group electrical characteristics (regular specifications) .............................. 432 15.2.1 power supply voltage and operating range....................................................... 432 15.2.2 dc characteristics ............................................................................................... 435 15.2.3 ac characteristics ............................................................................................... 441 15.2.4 a/d converter characteristics ............................................................................. 444 15.2.5 lcd characteristics............................................................................................. 446 15.3 h8/3827r group absolute maximum ratings (wide-range specification) ................... 448 15.4 h8/3827r group electrical characteristics (wide-range specification) ........................ 449 15.4.1 power supply voltage and operating range....................................................... 449 rev. 6.00 aug 04, 2006 page xx of xxxiv 15.4.2 dc characteristics ............................................................................................... 452 15.4.3 ac characteristics ............................................................................................... 458 15.4.4 a/d converter characteristics ............................................................................. 461 15.4.5 lcd characteristics............................................................................................. 463 15.5 h8/3827s group absolute maximum ratings ................................................................. 465 15.6 h8/3827s group electrical characteristics ...................................................................... 466 15.6.1 power supply voltage and operating range....................................................... 466 15.6.2 dc characteristics ............................................................................................... 468 15.6.3 ac characteristics ............................................................................................... 474 15.6.4 a/d converter characteristics ............................................................................. 477 15.6.5 lcd characteristics............................................................................................. 479 15.7 absolute maximum ratings of h8/38327 group and h8/38427 group .......................... 480 15.8 electrical characteristics of h8/38327 group and h8/38427 group................................ 481 15.8.1 power supply voltage and operating ranges ..................................................... 481 15.8.2 dc characteristics ............................................................................................... 484 15.8.3 ac characteristics ............................................................................................... 492 15.8.4 a/d converter characteristics ............................................................................. 495 15.8.5 lcd characteristics............................................................................................. 496 15.8.6 flash memory characteristics.............................................................................. 497 15.9 operation timing........................................................................................................... ... 499 15.10 output load circuit ....................................................................................................... ... 503 15.11 resonator ................................................................................................................. ......... 503 15.12 usage note................................................................................................................ ........ 504 appendix a cpu instruction set .................................................................................... 505 a.1 instructions................................................................................................................ ........ 505 a.2 operation code map......................................................................................................... 5 13 a.3 number of execution states.............................................................................................. 515 appendix b internal i/o registers ................................................................................. 520 b.1 addresses ................................................................................................................... ....... 520 b.2 functions................................................................................................................... ........ 525 appendix c i/o port block diagrams ........................................................................... 584 c.1 block diagrams of port 1.................................................................................................. 58 4 c.2 block diagrams of port 3.................................................................................................. 58 8 c.3 block diagrams of port 4.................................................................................................. 59 8 c.4 block diagram of port 5 ................................................................................................... 60 2 c.5 block diagram of port 6 ................................................................................................... 60 3 c.6 block diagram of port 7 ................................................................................................... 60 4 rev. 6.00 aug 04, 2006 page xxi of xxxiv c.7 block diagrams of port 8.................................................................................................. 60 5 c.8 block diagram of port a .................................................................................................. 606 c.9 block diagram of port b .................................................................................................. 607 appendix d port states in the different processing states ..................................... 608 appendix e list of product codes ................................................................................. 609 appendix f package dimensions .................................................................................. 614 appendix g specifications of chip form .................................................................... 617 appendix h form of bonding pads ............................................................................... 619 appendix i specifications of chip tray ...................................................................... 622 rev. 6.00 aug 04, 2006 page xxii of xxxiv figures section 1 overview figure 1.1 (1) block diagram (h8/3827r group and h8/3827s group)................................. 6 figure 1.1 (2) block diagram (h8/38327 group and h8/38427 group).................................. 7 figure 1.2 pin arrangement (fp-80a, tfp-80c: top view) ............................................. 9 figure 1.3 pin arrangement (fp-80b: top view) .............................................................. 10 figure 1.4 bonding pad location diagram of h8/3827r group (mask rom version) (top view)......................................................................................................... 11 figure 1.5 bonding pad location diagram of h8/3827s group (mask rom version) (top view)......................................................................................................... 15 figure 1.6 bonding pad location diagram of hcd64f38327 and hcd64f38427 (top view)......................................................................................................... 19 figure 1.7 bonding pad location diagram of h8/38327 group (mask rom version) and h8/38427 group (mask rom version) (top view) .................................. 23 section 2 cpu figure 2.1 cpu registers.................................................................................................... 34 figure 2.2 stack pointer ...................................................................................................... 35 figure 2.3 register data formats........................................................................................ 38 figure 2.4 memory data formats ....................................................................................... 39 figure 2.5 data transfer instruction codes ........................................................................ 49 figure 2.6 arithmetic, logic, and shift instruction codes ................................................. 53 figure 2.7 bit manipulation instruction codes ................................................................... 56 figure 2.8 branching instruction codes.............................................................................. 59 figure 2.9 system control instruction codes ..................................................................... 61 figure 2.10 block data transfer instruction code ............................................................... 62 figure 2.11 on-chip memory access cycle ........................................................................ 63 figure 2.12 on-chip peripheral module access cycle (2-state access) ............................. 64 figure 2.13 on-chip peripheral module access cycle (3-state access) ............................. 65 figure 2.14 cpu operation states ........................................................................................ 66 figure 2.15 state transitions................................................................................................. 67 figure 2.16(1) h8/3822r, h8/38322, and h8/38422 memory map ......................................... 68 figure 2.16(2) h8/3823r, h8/38323, and h8/38423 memory map ......................................... 69 figure 2.16(3) h8/3824r, h8/3824s, h8/38324, and h8/38424 memory map ....................... 70 figure 2.16(4) h8/3825r, h8/3825s, h8/38325, and h8/38425 memory map ....................... 71 figure 2.16(5) h8/3826r, h8/3826s, h8/38326, and h8/38426 memory map ....................... 72 figure 2.16(6) h8/3827r, h8/3827s, h8/38327, and h8/38427 memory map ....................... 73 rev. 6.00 aug 04, 2006 page xxiii of xxxiv figure 2.17 data size and number of states for access to and from on-chip peripheral modules ............................................................................................................. 75 figure 2.18 timer configuration example ........................................................................... 76 section 3 exception handling figure 3.1 reset sequence .................................................................................................. 84 figure 3.2 block diagram of interrupt controller .............................................................. 99 figure 3.3 flow up to interrupt acceptance....................................................................... 101 figure 3.4 stack state after completion of interrupt exception handling.......................... 102 figure 3.5 interrupt sequence ............................................................................................. 103 figure 3.6 operation when odd address is set in sp......................................................... 105 figure 3.7 port mode register setting and interrupt request flag clearing procedure..... 107 section 4 clock pulse generators figure 4.1 block diagram of clock pulse generators ........................................................ 109 figure 4.2 typical connection to crystal oscillator........................................................... 110 figure 4.3 typical connection to ceramic oscillator......................................................... 110 figure 4.4 board design of oscillator circuit .................................................................... 111 figure 4.5 external clock input (example) ........................................................................ 111 figure 4.6 typical connection to 32.768 khz/38.4 khz crystal oscillator (subclock) ..... 112 figure 4.7 equivalent circuit of 32.768 khz/38.4 khz crystal oscillator.......................... 112 figure 4.8 pin connection when not using subclock......................................................... 113 figure 4.9 (a) pin connection when inputting external clock................................................. 113 figure 4.9 (b) pin connection when inputting external clock (h8/38327 group and h8/38427 group)........................................................... 114 figure 4.10 example of crystal and ceramic oscillator element arrangement................... 116 figure 4.11 negative resistance measurement and circuit modification suggestions........ 117 figure 4.12 oscillation stabilization wait time................................................................... 118 section 5 power-down modes figure 5.1 mode transition diagram.................................................................................. 122 figure 5.2 standby mode transition and pin states ........................................................... 132 figure 5.3 external input signal capture when signal changes before/after standby mode or watch mode .......................................................................... 133 section 6 rom figure 6.1 rom block diagram (h8/3824r, h8/3824s, h8/38324, and h8/38424) ........ 145 figure 6.2 socket adapter pin correspondence (with hn27c101).................................... 147 figure 6.3 h8/3827r memory map in prom mode ......................................................... 148 figure 6.4 high-speed, high-reliability programming flow chart................................... 150 rev. 6.00 aug 04, 2006 page xxiv of xxxiv figure 6.5 prom write/verify timing.............................................................................. 153 figure 6.6 recommended screening procedure.................................................................. 155 figure 6.7 block diagram of flash memory ...................................................................... 157 figure 6.8 flash memory block configuration .................................................................. 158 figure 6.9 programming/erasing flowchart example in user program mode................... 169 figure 6.10 program/program-verify flowchart .................................................................. 171 figure 6.11 erase/erase-verify flowchart............................................................................ 174 figure 6.12 socket adapter pin correspondence diagram................................................... 178 figure 6.13 timing waveforms for memory read after memory write.............................. 179 figure 6.14 timing waveforms in transition from memory read mode to another mode 180 figure 6.15 ce and oe enable state read timing waveforms ........................................... 181 figure 6.16 ce and oe clock system read timing waveforms......................................... 181 figure 6.17 auto-program mode timing waveforms .......................................................... 183 figure 6.18 auto-erase mode timing waveforms............................................................... 185 figure 6.19 status read mode timing waveforms .............................................................. 186 figure 6.20 oscillation stabilization time, boot program transfer time, and power-down sequence ............................................................................... 188 section 7 ram figure 7.1 ram block diagram (h8/3824r, h8/3824s, h8/38324, and h8/38424) ........ 191 section 8 i/o ports figure 8.1 port 1 pin configuration .................................................................................... 195 figure 8.2 port 3 pin configuration .................................................................................... 203 figure 8.3 port 4 pin configuration .................................................................................... 212 figure 8.4 port 5 pin configuration .................................................................................... 215 figure 8.5 port 6 pin configuration .................................................................................... 219 figure 8.6 port 7 pin configuration .................................................................................... 223 figure 8.7 port 8 pin configuration .................................................................................... 226 figure 8.8 port a pin configuration ................................................................................... 229 figure 8.9 port b pin configuration.................................................................................... 232 figure 8.10 input/output data inversion function ............................................................... 233 section 9 timers figure 9.1 block diagram of timer a ................................................................................ 239 figure 9.2 block diagram of timer c ................................................................................ 248 figure 9.3 block diagram of timer f................................................................................. 257 figure 9.4 write access to tcr (cpu tcf)................................................................. 267 figure 9.5 read access to tcf (tcf cpu) .................................................................. 268 figure 9.6 tmofh/tmofl output timing ...................................................................... 270 rev. 6.00 aug 04, 2006 page xxv of xxxiv figure 9.7 clear interrupt request flag when interrupt factor generation signal is valid .................................................................................................................. 274 figure 9.8 block diagram of timer g ................................................................................ 277 figure 9.9 noise canceler block diagram.......................................................................... 284 figure 9.10 noise canceler timing (example)..................................................................... 285 figure 9.11 input capture input timing (without noise cancellation function) ................. 287 figure 9.12 input capture input timing (with noise cancellation function) ...................... 288 figure 9.13 timing of input capture by input capture input ............................................... 288 figure 9.14 tcg clear timing ............................................................................................. 289 figure 9.15 port mode register manipulation and interrupt enable flag clearing procedure ........................................................................................................... 295 figure 9.16 timer g application example ........................................................................... 295 figure 9.17 block diagram of watchdog timer................................................................... 296 figure 9.18 typical watchdog timer operations (example) ............................................... 302 figure 9.19 block diagram of asynchronous event counter............................................... 304 figure 9.20 example of software processing when using ech and ecl as 16-bit event counter............................................................................................................... 310 figure 9.21 example of software processing when using ech and ecl as 8-bit event counters ............................................................................................................. 311 section 10 serial communication interface figure 10.1 sci3 block diagram.......................................................................................... 317 figure 10.2 (a) rdrf setting and rxi interrupt ....................................................................... 344 figure 10.2 (b) tdre setting and txi interrupt ....................................................................... 344 figure 10.2 (c) tend setting and tei interrupt........................................................................ 344 figure 10.3 data format in asynchronous communication................................................. 345 figure 10.4 phase relationship between output clock and transfer data (asynchronous mode) (8-bit data, parity, 2 stop bits) ....................................... 347 figure 10.5 example of sci3 initialization flowchart ......................................................... 348 figure 10.6 example of data transmission flowchart (asynchronous mode) .................... 349 figure 10.7 example of operation when transmitting in asynchronous mode (8-bit data, parity, 1 stop bit).............................................................................. 350 figure 10.8 example of data reception flowchart (asynchronous mode) ......................... 351 figure 10.9 example of operation when receiving in asynchronous mode (8-bit data, parity, 1 stop bit).............................................................................. 354 figure 10.10 data format in synchronous communication ................................................... 355 figure 10.11 example of data transmission flowchart (synchronous mode) ...................... 356 figure 10.12 example of operation when transmitting in synchronous mode..................... 357 figure 10.13 example of data reception flowchart (synchronous mode)............................ 358 figure 10.14 example of operation when receiving in synchronous mode ......................... 359 rev. 6.00 aug 04, 2006 page xxvi of xxxiv figure 10.15 example of simultaneous data transmission/reception flowchart (synchronous mode).......................................................................................... 360 figure 10.16 example of inter-processor communication using multiprocessor format (sending data h'aa to receiver a).................................................................. 362 figure 10.17 example of multiprocessor data transmission flowchart ................................ 363 figure 10.18 example of operation when transmitting using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit) .......................................................... 364 figure 10.19 example of multiprocessor data reception flowchart ..................................... 365 figure 10.20 example of operation when receiving using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit) .......................................................... 367 figure 10.21 receive data sampling timing in asynchronous mode................................... 371 figure 10.22 relation between rdr read timing and data ................................................. 372 section 11 14-bit pwm figure 11.1 block diagram of the 14 bit pwm ................................................................... 376 figure 11.2 pwm output waveform.................................................................................... 381 section 12 a/d converter figure 12.1 block diagram of the a/d converter ................................................................ 384 figure 12.2 external trigger input timing........................................................................... 390 figure 12.3 typical a/d converter operation timing ......................................................... 393 figure 12.4 flow chart of procedure for using a/d converter (polling by software)........ 394 figure 12.5 flow chart of procedure for using a/d converter (interrupts used) ............... 395 figure 12.6 analog input circuit example ........................................................................... 397 section 13 lcd controller/driver figure 13.1 block diagram of lcd controller/driver ......................................................... 400 figure 13.2 example of a waveform with 1/2 duty and 1/2 bias ....................................... 407 figure 13.3 handling of lcd drive power supply when using 1/2 duty........................... 409 figure 13.4 examples of lcd power supply pin connections ............................................ 410 figure 13.5 lcd ram map when not using segment external expansion (1/4 duty) ..... 412 figure 13.6 lcd ram map when not using segment external expansion (1/3 duty) ..... 413 figure 13.7 lcd ram map when not using segment external expansion (1/2 duty) ..... 414 figure 13.8 lcd ram map when not using segment external expansion (static mode) 414 figure 13.9 lcd ram map when using segment external expansion (sgx = ?1?, sgs3 to sgs0 = ?0000? 1/4 duty)............................................... 415 figure 13.10 lcd ram map when using segment external expansion (sgx = ?1?, sgs3 to sgs0 = ?0000? 1/3 duty)............................................... 416 figure 13.11 lcd ram map when using segment external expansion (sgx = ?1?, sgs3 to sgs0 = ?0000? 1/2 duty)............................................... 417 rev. 6.00 aug 04, 2006 page xxvii of xxxiv figure 13.12 lcd ram map when using segment external expansion (sgx = ?1?, sgs3 to sgs0 = ?0000? static).................................................... 418 figure 13.13 lcd drive power supply unit .......................................................................... 419 figure 13.14 example of low-power-consumption lcd drive operation........................... 421 figure 13.15 output waveforms for each duty cycle (a waveform)................................... 422 figure 13.16 output waveforms for each duty cycle (b waveform)................................... 423 figure 13.17 connection of external split-resistance............................................................ 425 figure 13.18 connection to hd66100 .................................................................................... 427 section 14 power supply circuit figure 14.1 power supply connection when internal step-down circuit is used............... 429 figure 14.2 power supply connection when internal step-down circuit is not used........ 430 section 15 electrical characteristics figure 15.1 clock input timing............................................................................................ 499 figure 15.2 res low width................................................................................................. 499 figure 15.3 input timing ...................................................................................................... 49 9 figure 15.4 ud pin minimum modulation width timing ................................................... 500 figure 15.5 sck3 input clock timing ................................................................................. 500 figure 15.6 sci3 synchronous mode input/output timing ................................................. 501 figure 15.7 segment expansion signal timing.................................................................... 502 figure 15.8 output load condition ...................................................................................... 503 figure 15.9 resonator equivalent circuit ............................................................................. 503 figure 15.10 resonator equivalent circuit ............................................................................. 504 appendix c i/o port block diagrams figure c.1 (a) port 1 block diagram (pins p1 7 to p1 4 )............................................................. 584 figure c.1 (b) port 1 block diagram (pin p1 3 )......................................................................... 585 figure c.1 (c) port 1 block diagram (pin p1 2 , p1 1 ) ................................................................. 586 figure c.1 (d) port 1 block diagram (pin p1 0 )......................................................................... 587 figure c.2 (a) port 3 block diagram (pin p3 7 to p3 6 ) .............................................................. 588 figure c.2 (b) port 3 block diagram (pin p3 5 )......................................................................... 589 figure c.2 (c) port 3 block diagram (pin p3 4 )......................................................................... 590 figure c.2 (d) port 3 block diagram (pin p3 3 )......................................................................... 591 figure c.2 (e-1)port 3 block diagram (pin p3 2 , h8/3827r group and h8/3827s group) ........ 592 figure c.2 (e-2)port 3 block diagram (pin p3 2 in the mask rom version of the h8/38327 group and h8/38427 group) ........................................................................................ 593 figure c.2 (e-3)port 3 block diagram (pin p3 2 in the f-ztat version of the h8/38327 group and h8/38427 group) ........................................................................................ 594 figure c.2 (f-1) port 3 block diagram (pin p3 1 , h8/3827r group and h8/3827s group) ........ 595 rev. 6.00 aug 04, 2006 page xxviii of xxxiv figure c.2 (f-2) port 3 block diagram (pin p3 1 , h8/38327 group and h8/38427 group) ......... 596 figure c.2 (g) port 3 block diagram (pin p3 0 )......................................................................... 597 figure c.3 (a) port 4 block diagram (pin p4 3 )......................................................................... 598 figure c.3 (b) port 4 block diagram (pin p4 2 )......................................................................... 599 figure c.3 (c) port 4 block diagram (pin p4 1 )......................................................................... 600 figure c.3 (d) port 4 block diagram (pin p4 0 )......................................................................... 601 figure c.4 port 5 block diagram ........................................................................................ 602 figure c.5 port 6 block diagram ........................................................................................ 603 figure c.6 port 7 block diagram ........................................................................................ 604 figure c.7 port 8 block diagram ........................................................................................ 605 figure c.8 port a block diagram........................................................................................ 606 figure c.9 port b block diagram........................................................................................ 607 appendix f package dimensions figure f.1 fp-80a package dimensions............................................................................. 614 figure f.2 fp-80b package dimensions............................................................................. 615 figure f.3 tfp-80c package dimensions .......................................................................... 616 appendix g specifications of chip form figure g.1 chip sectional figure ........................................................................................ 617 figure g.2 chip sectional figure ........................................................................................ 617 figure g.3 chip sectional figure ........................................................................................ 618 figure g.4 chip sectional figure ........................................................................................ 618 appendix h form of bonding pads figure h.1 bonding pad form ............................................................................................. 619 figure h.2 bonding pad form ............................................................................................. 620 figure h.3 bonding pad form ............................................................................................. 621 appendix i specifications of chip tray figure i.1 specifications of chip tray ............................................................................... 622 figure i.2 specifications of chip tray ............................................................................... 623 figure i.3 specifications of chip tray ............................................................................... 624 figure i.4 specifications of chip tray ............................................................................... 625 rev. 6.00 aug 04, 2006 page xxix of xxxiv tables section 1 overview table 1.1 features .............................................................................................................. .... 2 table 1.2 bonding pad coordinates of h8/3827r group (mask rom version).................. 12 table 1.3 bonding pad coordinates of h8/3827s group (mask rom version) .................. 16 table 1.4 bonding pad coordinates of hcd64f38327 and hcd64f38427......................... 20 table 1.5 bonding pad coordinates of h8/38327 group (mask rom version) and h8/38427 group (mask rom version)................................................................. 24 table 1.6 pin functions......................................................................................................... .27 section 2 cpu table 2.1 addressing modes.................................................................................................. 40 table 2.2 effective address calculation................................................................................ 43 table 2.3 instruction set ....................................................................................................... .46 table 2.4 data transfer instructions ...................................................................................... 48 table 2.5 arithmetic instructions........................................................................................... 50 table 2.6 logic operation instructions.................................................................................. 51 table 2.7 shift instructions .................................................................................................... 52 table 2.8 bit-manipulation instructions ................................................................................ 54 table 2.9 branching instructions ........................................................................................... 58 table 2.10 system control instructions ................................................................................... 60 table 2.11 block data transfer instruction ............................................................................. 62 table 2.12 registers with shared addresses............................................................................ 81 table 2.13 registers with write-only bits .............................................................................. 81 section 3 exception handling table 3.1 exception handling types and priorities............................................................... 83 table 3.2 interrupt sources and their priorities .................................................................... 86 table 3.3 interrupt control registers ..................................................................................... 87 table 3.4 interrupt wait states............................................................................................... 10 4 table 3.5 conditions under which interrupt request flag is set to 1 ................................... 106 section 5 power-down modes table 5.1 operating modes .................................................................................................... 121 table 5.2 internal state in each operating mode .................................................................. 123 table 5.3 system control registers ....................................................................................... 124 table 5.4 clock frequency and settling time (times are in ms) .......................................... 131 table 5.5 setting and clearing module standby mode by clock stop register.................... 143 rev. 6.00 aug 04, 2006 page xxx of xxxiv section 6 rom table 6.1 setting to prom mode.......................................................................................... 146 table 6.2 socket adapter ....................................................................................................... 1 46 table 6.3 mode selection in prom mode (h8/3827r)........................................................ 149 table 6.4 dc characteristics.................................................................................................. 15 1 table 6.5 ac characteristics.................................................................................................. 15 2 table 6.6 register configuration ........................................................................................... 159 table 6.7 division of blocks to be erased ............................................................................ 163 table 6.8 setting programming modes.................................................................................. 166 table 6.9 boot mode operation............................................................................................. 168 table 6.10 oscillating frequencies (f osc ) for which automatic adjustment of lsi bit rate is possible............................................................................................................... 168 table 6.11 reprogram data computation table...................................................................... 172 table 6.12 additional-program data computation table ....................................................... 172 table 6.13 programming time................................................................................................. 172 table 6.14 command sequence in programmer mode............................................................ 177 table 6.15 ac characteristics in transition to memory read mode ...................................... 179 table 6.16 ac characteristics in transition from memory read mode to another mode ..... 180 table 6.17 ac characteristics in memory read mode ........................................................... 181 table 6.18 ac characteristics in auto-program mode ........................................................... 183 table 6.19 ac characteristics in auto-erase mode ................................................................ 184 table 6.20 ac characteristics in status read mode ............................................................... 186 table 6.21 status read mode return codes............................................................................ 187 table 6.22 status polling output truth table.......................................................................... 187 table 6.23 stipulated transition times to command wait state ............................................ 188 table 6.24 flash memory operating states ............................................................................. 189 section 8 i/o ports table 8.1 port functions ........................................................................................................ 193 table 8.2 port 1 registers ...................................................................................................... 195 table 8.3 port 1 pin functions ............................................................................................... 200 table 8.4 port 1 pin states ..................................................................................................... 202 table 8.5 port 3 registers ...................................................................................................... 203 table 8.6 port 3 pin functions ............................................................................................... 209 table 8.7 port 3 pin states ..................................................................................................... 211 table 8.8 port 4 registers ...................................................................................................... 212 table 8.9 port 4 pin functions ............................................................................................... 214 table 8.10 port 4 pin states .................................................................................................... . 215 table 8.11 port 5 registers ..................................................................................................... . 216 table 8.12 port 5 pin functions ............................................................................................... 21 8 rev. 6.00 aug 04, 2006 page xxxi of xxxiv table 8.13 port 5 pin states .................................................................................................... . 218 table 8.14 port 6 registers ..................................................................................................... . 220 table 8.15 port 6 pin functions ............................................................................................... 22 1 table 8.16 port 6 pin states .................................................................................................... . 222 table 8.17 port 7 registers ..................................................................................................... . 223 table 8.18 port 7 pin functions ............................................................................................... 22 5 table 8.19 port 7 pin states .................................................................................................... . 225 table 8.20 port 8 registers ..................................................................................................... . 226 table 8.21 port 8 pin functions ............................................................................................... 22 8 table 8.22 port 8 pin states .................................................................................................... . 229 table 8.23 port a registers ..................................................................................................... 230 table 8.24 port a pin functions .............................................................................................. 231 table 8.25 port a pin states .................................................................................................... 232 table 8.26 port b register ...................................................................................................... . 233 table 8.27 register configuration ........................................................................................... 234 section 9 timers table 9.1 timer functions ..................................................................................................... 23 7 table 9.2 pin configuration ................................................................................................... 23 9 table 9.3 timer a registers .................................................................................................. 240 table 9.4 timer a operation states....................................................................................... 246 table 9.5 pin configuration ................................................................................................... 24 8 table 9.6 timer c registers................................................................................................... 24 9 table 9.7 timer c operation states ....................................................................................... 254 table 9.8 pin configuration ................................................................................................... 25 8 table 9.9 timer f registers ................................................................................................... 25 8 table 9.10 timer f operation modes ...................................................................................... 271 table 9.11 pin configuration ................................................................................................... 2 78 table 9.12 timer g registers .................................................................................................. 27 8 table 9.13 timer g operation modes ..................................................................................... 290 table 9.14 internal clock switching and tcg operation ....................................................... 291 table 9.15 input capture input signal input edges due to input capture input pin switching, and conditions for their occurrence ................................................... 293 table 9.16 input capture input signal input edges due to noise canceler function switching, and conditions for their occurrence ................................................... 294 table 9.17 watchdog timer registers ..................................................................................... 297 table 9.18 watchdog timer operation states ......................................................................... 302 table 9.19 pin configuration ................................................................................................... 3 04 table 9.20 asynchronous event counter registers ................................................................. 305 table 9.21 asynchronous event counter operation modes .................................................... 311 rev. 6.00 aug 04, 2006 page xxxii of xxxiv section 10 serial communication interface table 10.1 pin configuration ................................................................................................... 3 18 table 10.2 registers ............................................................................................................ ..... 318 table 10.3 examples of brr settings for various bit rates (asynchronous mode) (1)........ 333 table 10.3 examples of brr settings for various bit rates (asynchronous mode) (2)........ 334 table 10.4 relation between n and clock................................................................................ 335 table 10.5 maximum bit rate for each frequency (asynchronous mode)............................ 335 table 10.6 examples of brr settings for various bit rates (synchronous mode)................ 336 table 10.7 relation between n and clock................................................................................ 337 table 10.8 smr settings and corresponding data transfer formats ..................................... 341 table 10.9 smr and scr3 settings and clock source selection ........................................... 342 table 10.10 transmit/receive interrupts ................................................................................... 343 table 10.11 data transfer formats (asynchronous mode) ....................................................... 346 table 10.12 receive error detection conditions and receive data processing........................ 353 table 10.13 sci3 interrupt requests ......................................................................................... 368 table 10.14 ssr status flag states and receive data transfer ................................................ 369 section 11 14-bit pwm table 11.1 pin configuration ................................................................................................... 3 76 table 11.2 register configuration ........................................................................................... 377 table 11.3 pwm operation modes.......................................................................................... 381 section 12 a/d converter table 12.1 pin configuration ................................................................................................... 3 85 table 12.2 register configuration ........................................................................................... 385 table 12.3 a/d converter operation modes ........................................................................... 391 section 13 lcd controller/driver table 13.1 pin configuration ................................................................................................... 4 01 table 13.2 lcd controller/driver registers ........................................................................... 401 table 13.3 output levels ........................................................................................................ . 424 table 13.4 power-down modes and display operation.......................................................... 425 section 15 electrical characteristics table 15.1 absolute maximum ratings................................................................................... 431 table 15.2 dc characteristics.................................................................................................. 4 35 table 15.3 control signal timing............................................................................................ 441 table 15.4 serial interface (sci3-1, sci3-2) timing .............................................................. 443 table 15.5 a/d converter characteristics ............................................................................... 444 table 15.6 lcd characteristics ............................................................................................... 446 rev. 6.00 aug 04, 2006 page xxxiii of xxxiv table 15.7 ac characteristics for external segment expansion............................................. 447 table 15.8 absolute maximum ratings................................................................................... 448 table 15.9 dc characteristics.................................................................................................. 4 52 table 15.10 control signal timing............................................................................................ 458 table 15.11 serial interface (sci3-1, sci3-2) timing .............................................................. 460 table 15.12 a/d converter characteristics ............................................................................... 461 table 15.13 lcd characteristics ............................................................................................... 46 3 table 15.14 ac characteristics for external segment expansion............................................. 464 table 15.15 absolute maximum ratings................................................................................... 465 table 15.16 dc characteristics.................................................................................................. 468 table 15.17 control signal timing............................................................................................ 474 table 15.18 serial interface (sci3-1, sci3-2) timing .............................................................. 476 table 15.19 a/d converter characteristics ............................................................................... 477 table 15.20 lcd characteristics ............................................................................................... 47 9 table 15.21 ac characteristics for external segment expansion............................................. 479 table 15.22 absolute maximum ratings................................................................................... 480 table 15.23 dc characteristics.................................................................................................. 484 table 15.24 control signal timing............................................................................................ 492 table 15.25 serial interface (sci3) timing............................................................................... 494 table 15.26 a/d converter characteristics ............................................................................... 495 table 15.27 lcd characteristics ............................................................................................... 49 6 table 15.28 flash memory characteristics................................................................................ 497 appendix a cpu instruction set table a.1 instruction set ....................................................................................................... . 506 table a.2 operation code map .............................................................................................. 514 table a.3 number of cycles in each instruction ................................................................... 515 table a.4 number of cycles in each instruction ................................................................... 516 appendix d port states in the different processing states table d.1 port states overview .............................................................................................. 608 appendix e list of product codes table e.1 h8/3827r group, h8/3827s group, and h8/38327 group product code lineup .................................................................................................................. 609 rev. 6.00 aug 04, 2006 page xxxiv of xxxiv section 1 overview rev. 6.00 aug 04, 2006 page 1 of 626 rej09b0144-0600 section 1 overview 1.1 overview the h8/300l series is a series of single-chip microcomputers (mcu: microcomputer unit), built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. within the h8/300l series, the h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group comprise single-chip microcomputers equipped with an lcd (liquid crystal display) controller/driver. other on-chip peripheral functions include six timers, a 14-bit pulse width modulator (pwm), two serial communication interface channels, and an a/d converter. together, these functions make the h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group ideally suited for embedded applications in systems requiring low power consumption and lcd display. also available are models incorporating 16 kbytes to 60 kbytes of rom and 1 kbyte to 2 kbytes of ram on-chip. the h8/3827r is also available in a ztat? * 1 version with on-chip prom which can be programmed as required by the user. the h8/38327 and h8/38427 are available in a f-ztat? * 2 version with on-chip flash memory that can be programmed on-board. table 1.1 summarizes the features of the h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group. notes: 1. ztat (zero turn around time) is a trademark of renesas technology corp. 2. f-ztat is a trademark of renesas technology corp. section 1 overview rev. 6.00 aug 04, 2006 page 2 of 626 rej09b0144-0600 table 1.1 features item description cpu high-speed h8/300l cpu ? general-register architecture general registers: sixteen 8-bit registers (can be used as eight 16-bit registers) ? operating speed ? max. operating speed: 8 mhz ? add/subtract: 0.25 s (operating at 8 mhz) ? multiply/divide: 1.75 s (operating at 8 mhz) ? can run on 32.768 khz or 38.4 khz subclock ? instruction set compatible with h8/300 cpu ? instruction length of 2 bytes or 4 bytes ? basic arithmetic operations between registers ? mov instruction for data transfer between memory and registers ? typical instructions ? multiply (8 bits 8 bits) ? divide (16 bits 8 bits) ? bit accumulator ? register-indirect designation of bit position interrupts 36 interrupt sources ? 13 external interrupt sources (irq 4 to irq 0 , wkp 7 to wkp 0 ) ? 23 internal interrupt sources clock pulse generators two on-chip clock pulse generators ? system clock pulse generator: ? maximum 16 mhz (h8/3827r, h8/38327, h8/38427 group) ? maximum 10 mhz (h8/3827s group) ? subclock pulse generator: 32.768 khz, 38.4 khz section 1 overview rev. 6.00 aug 04, 2006 page 3 of 626 rej09b0144-0600 item description power-down modes seven power-down modes ? sleep (high-speed) mode ? sleep (medium-speed) mode ? standby mode ? watch mode ? subsleep mode ? subactive mode ? active (medium-speed) mode memory large on-chip memory ? h8/3822r, h8/38322, h8/38422: 16-kbyte rom, 1-kbyte ram ? h8/3823r, h8/38323, h8/38423: 24-kbyte rom, 1-kbyte ram ? h8/3824r, h8/3824s, h8/38324, h8/38424: 32-kbyte rom, 2-kbyte ram ? h8/3825r, h8/3825s, h8/38325, h8/38425: 40-kbyte rom, 2-kbyte ram ? h8/3826r, h8/3826s, h8/38326, h8/38426: 48-kbyte rom, 2-kbyte ram ? h8/3827r, h8/3827s, h8/38327, h8/38427: 60-kbyte rom, 2-kbyte ram i/o ports 64 pins ? 55 i/o pins ? 9 input pins section 1 overview rev. 6.00 aug 04, 2006 page 4 of 626 rej09b0144-0600 item description timers six on-chip timers ? timer a: 8-bit timer count-up timer with selection of eight internal clock signals divided from the system clock ( ) * and four clock signals divided from the watch clock ( w ) * ? asynchronous event counter: 16-bit timer ? count-up timer able to count asynchronous external events independently of the mcu's internal clocks ? timer c: 8-bit timer ? count-up/down timer with selection of seven internal clock signals or event input from external pin ? auto-reloading ? timer f: 16-bit timer ? can be used as two independent 8-bit timers ? count-up timer with selection of four internal clock signals or event input from external pin ? provision for toggle output by means of compare-match function ? timer g: 8-bit timer ? count-up timer with selection of four internal clock signals ? incorporates input capture function (built-in noise canceler) ? watchdog timer ? reset signal generated by overflow of 8-bit counter serial communication interface two serial communication interface channels on chip ? sci3-1: 8-bit synchronous/asynchronous serial interface incorporates multiprocessor communication function ? sci3-2: 8-bit synchronous/asynchronous serial interface incorporates multiprocessor communication function 14-bit pwm pulse-division pwm output for reduced ripple ? can be used as a 14-bit d/a converter by connecting to an external low-pass filter. a/d converter successive approximations using a resistance ladder ? 8-channel analog input pins ? conversion time: 31/ or 62/ per channel section 1 overview rev. 6.00 aug 04, 2006 page 5 of 626 rej09b0144-0600 item description lcd controller/driver lcd controller/driver equipped with a maximum of 32 segment pins and four common pins ? choice of four duty cycles (static, 1/2, 1/3, or 1/4) ? segment pins can be switched to general-purpose port function in 8- bit units product lineup mask rom version ztat version f-ztat version package rom/ram size (byte) hd6433827r hd6433827s hd64338327 hd64338427 hd6473827r hd64f38327 hd64f38427 fp-80b (h8/3827r only) fp-80a tfp-80c die 60 k/2 k hd6433826r hd6433826s hd64338326 hd64338426 ?? fp-80b (h8/3826r only) fp-80a tfp-80c die 48 k/2 k hd6433825r hd6433825s hd64338325 hd64338425 ?? fp-80b (h8/3825r only) fp-80a tfp-80c die 40 k/2 k hd6433824r HD6433824S hd64338324 hd64338424 ? hd64f38324 hd64f38424 fp-80b (h8/3824r only) fp-80a tfp-80c die (mask rom version only) 32 k/2 k hd6433823r hd64338323 hd64338423 ?? fp-80b (h8/3823r only) fp-80a tfp-80c die 24 k/1 k hd6433822r hd64338322 hd64338422 ?? fp-80b (h8/3822r only) fp-80a tfp-80c die 16 k/1 k see appendix e for a list of product codes. note: * see section 4, clock pulse generators, for the definition of and w . section 1 overview rev. 6.00 aug 04, 2006 page 6 of 626 rej09b0144-0600 1.2 internal block diagram figure 1.1(1) shows a block diagram of the h8/3827r group and h8/3827s group. figure 1.1(2) shows a block diagram of the h8/38327 group and h8/38427 group. p1 0 /tmow p1 1 /tmofl p1 2 /tmofh p1 3 /tmig p1 4 / irq 4 / adtrg p1 5 / irq 1 /tmic p1 6 / irq 2 p1 7 / irq 3 /tmif p3 0 /pwm p3 1 /ud p3 2 / reso p3 3 /sck 31 p3 4 /rxd 31 p3 5 /txd 31 p3 6 /aevh p3 7 /aevl p5 0 / wkp 0 /seg 1 p5 1 / wkp 1 /seg 2 p5 2 / wkp 2 /seg 3 p5 3 / wkp 3 /seg 4 p5 4 / wkp 4 /seg 5 p5 5 / wkp 5 /seg 6 p5 6 / wkp 6 /seg 7 p5 7 / wkp 7 /seg 8 p4 0 /sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / irq 0 osc 1 osc 2 system clock osc port 1 port a port 8 port 7 port 6 port 3 port 4 port 5 x 1 x 2 sub clock osc v ss v ss v cc cv cc * res test h8/300l cpu lcd power supply rom (60k/48k/40k/32k 24k/16k) ram (2k/1k) timer a timer c timer f timer g asynchronous counter serial communication interface 3-1 serial communication interface 3-2 14-bit pwm wdt lcd controller a/d (10bit) v 0 v 1 v 2 v 3 pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 p8 7 /seg 32 /cl 1 p8 6 /seg 31 /cl 2 p8 5 /seg 30 /do p8 4 /seg 29 /m p8 3 /seg 28 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 port b note: * v cc in the h8/3827s av cc av ss pb 0 /an 0 pb 1 /an 1 pb 2 /an 2 pb 3 /an 3 pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 figure 1.1(1) block diagram (h8/3827r group and h8/3827s group) section 1 overview rev. 6.00 aug 04, 2006 page 7 of 626 rej09b0144-0600 p1 0 /tmow p1 1 /tmofl p1 2 /tmofh p1 3 /tmig p1 4 / irq 4 / adtrg p1 5 / irq 1 /tmic p1 6 / irq 2 p1 7 / irq 3 /tmif p3 0 /pwm p3 1 /ud/excl p3 2 p3 3 /sck 31 p3 4 /rxd 31 p3 5 /txd 31 p3 6 /aevh p3 7 /aevl p5 0 / wkp 0 /seg 1 p5 1 / wkp 1 /seg 2 p5 2 / wkp 2 /seg 3 p5 3 / wkp 3 /seg 4 p5 4 / wkp 4 /seg 5 p5 5 / wkp 5 /seg 6 p5 6 / wkp 6 /seg 7 p5 7 / wkp 7 /seg 8 p4 0 /sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / irq 0 osc 1 osc 2 system clock osc port 1 port a port 8 port 7 port 6 port 3 port 4 port 5 x 1 x 2 sub clock osc v ss v ss v cc cv cc res test h8/300l cpu lcd power supply rom (60k/48k/40k/32k 24k/16k) ram (2k/1k) timer a timer c timer f timer g asynchronous counter serial communication interface 3-1 serial communication interface 3-2 14-bit pwm wdt lcd controller a/d (10bit) v 0 v 1 v 2 v 3 pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 p8 7 /seg 32 p8 6 /seg 31 p8 5 /seg 30 p8 4 /seg 29 p8 3 /seg 28 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 port b note: when the on-chip emulator is used, pins p3 2 , p8 5 , p8 6 , and p8 7 are reserved for use exclusively by the emulator and therefore cannot be accessed by the user. av cc av ss pb 0 /an 0 pb 1 /an 1 pb 2 /an 2 pb 3 /an 3 pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 figure 1.1(2) block diagram (h8/38327 group and h8/38427 group) section 1 overview rev. 6.00 aug 04, 2006 page 8 of 626 rej09b0144-0600 1.3 pin arrangement and functions 1.3.1 pin arrangement the pin arrangements of the h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group are shown in figures 1.2 and 1.3 (figure 1.3 only applies to the h8/3827r group). the bonding pad location diagram of the h8/3827r group (mask rom version) is shown in figure 1.4, and the bonding pad coordinates are given in table 1.2. the bonding pad location diagram of the h8/3827s group (mask rom version) is shown in figure 1.5, and the bonding pad coordinates are given in table 1.3. the bonding pad location diagram of the hcd64f38327 and hcd64f38427 is shown in figure 1.6, and the bonding pad coordinates are given in table 1.4. the bonding pad location diagram of the h8/38327 group (mask rom version) and h8/38427 group (mask rom version) is shown in figure 1.7, and the bonding pad coordinates are given in table 1.5. section 1 overview rev. 6.00 aug 04, 2006 page 9 of 626 rej09b0144-0600 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 p5 7 / wkp 7 /seg 8 p5 6 / wkp 6 /seg 7 p5 5 / wkp 5 /seg 6 p5 4 / wkp 4 /seg 5 p8 0 /seg 25 p8 1 /seg 26 p8 2 /seg 27 p8 3 /seg 28 p8 4 /seg 29 /m (p8 4 /seg 29 * ) p8 5 /seg 30 /do (p8 5 /seg 30 * ) p8 6 /seg 31 /cl 2 (p8 6 /seg 31 * ) p8 7 /seg 32 /cl 1 (p8 7 /seg 32 * ) p4 0/ sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / irq 0 av cc pb 0 /an 0 pb 1 /an 1 pb 2 /an 2 pb 3 /an 3 pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 notes: when the on-chip emulator is used, pins p3 2 , p8 5 , p8 6 , and p8 7 are reserved for use exclusively by the emulator and therefore cannot be accessed by the user. * h8/38327, h8/38427 pb 7 /an 7 av ss x 1 x 2 v ss osc 2 osc 1 test res p1 0 /tmow p1 1 /tmofl p1 2 /tmofh p1 3 /tmig p1 4 / irq 4 / adtrg p1 5 / irq 1 /tmic p1 6 / irq 2 p1 7 / irq 3 /tmif p3 0 /pwm p3 1 /ud (p3 1 /ud/excl * ) p3 2 / reso (p3 2 * ) p5 3 / wkp 3 /seg 4 p5 2 / wkp 2 /seg 3 p5 1 / wkp 1 /seg 2 p5 0 / wkp 0 /seg 1 pa 0 /com1 pa 1 /com2 pa 2 /com3 pa 3 /com4 v cc v0 v1 v2 v3 v ss cv cc (v cc in the h8/3827s) p3 7 /aevl p3 6 /aevh p3 5 /txd 31 p3 4 /rxd 31 p3 3 /sck 31 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 12 3 45 6 78 9 10 11 12 13 14 15 16 17 18 19 20 figure 1.2 pin arrangement (fp-80a, tfp-80c: top view) section 1 overview rev. 6.00 aug 04, 2006 page 10 of 626 rej09b0144-0600 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 av ss x 1 x 2 v ss osc 2 osc 1 test res p1 0 /tmow p1 1 /tmofl p1 2 /tmofh p1 3 /tmig p1 4 / irq 4 / adtrg p1 5 / irq 1 /tmic p1 6 / irq 2 p1 7 / irq 3 /tmif p3 0 /pwm p3 1 /ud p3 2 / reso p3 3 /sck 31 p3 4 /rxd 31 54 p8 1 /seg 26 p8 0 /seg 25 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 p5 7 / wkp 7 /seg 8 p5 6 / wkp 6 /seg 7 p5 5 / wkp 5 /seg 6 p5 4 / wkp 4 /seg 5 p5 3 / wkp 3 /seg 4 p5 2 / wkp 2 /seg 3 p8 2 /seg 27 p8 3 /seg 28 p8 4 /seg 29 /m p8 5 /seg 30 /do p8 6 /seg 31 /cl 2 p8 7 /seg 32 /cl 1 p4 0 /sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / irq 0 av cc pb 0 /an 0 pb 1 /an 1 pb 2 /an 2 pb 3 /an 3 pb 4 /an 4 p5 1 / wkp 1 /seg 2 p5 0 / wkp 0 /seg 1 pa 0 /com1 pa 1 /com2 pa 2 /com3 pa 3 /com4 v cc v0 v1 v2 v3 v ss cv cc p3 7 /aevl p3 6 /aevh p3 5 /txd 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 101112131415161718192021222324 figure 1.3 pin arrangement (fp-80b: top view) section 1 overview rev. 6.00 aug 04, 2006 page 11 of 626 rej09b0144-0600 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 7170 69 68 67 66 65 64 63 62 61 x y (0, 0) type code : nc pad chip size : 6.10mm 6.23mm voltage level on the back of the chip : gnd figure 1.4 bonding pad location diagram of h8/3827r group (mask rom version) (top view) section 1 overview rev. 6.00 aug 04, 2006 page 12 of 626 rej09b0144-0600 table 1.2 bonding pad coordinates of h8/3827r group (mask rom version) coordinates * pad no. pad name x (m) y (m) 1pb 7 /an 7 -2866 2382 2 avss -2866 2193 3x 1 -2866 1694 4x 2 -2866 1500 5 vss -2866 1156 6osc 2 -2866 810 7osc 1 -2866 636 8 test -2866 288 9 res -2866 116 10 p1 0 /tmow -2866 -228 11 p1 1 /tmofl -2866 -402 12 p1 2 /tmofh -2866 -576 13 p1 3 /tmig -2866 -920 14 p1 4 / irq 4 / adtrg -2866 -1094 15 p1 5 / irq 1 /tmic -2866 -1266 16 p1 6 / irq 2 -2866 -1440 17 p1 7 / irq 3 /tmif -2866 -1785 18 p3 0 /pwm -2866 -1969 19 p3 1 /ud -2866 -2327 20 p3 2 / reso -2866 -2503 21 p3 3 /sck 31 -2669 -2931 22 p3 4 /rxd 31 -2142 -2931 23 p3 5 /txd 31 -1971 -2931 24 p3 6 /aevh -1798 -2931 25 p3 7 /aevl -1624 -2931 26 cvcc -1413 -2931 27 vss -1213 -2931 28 v3 -1017 -2931 29 v2 -844 -2931 section 1 overview rev. 6.00 aug 04, 2006 page 13 of 626 rej09b0144-0600 coordinates * pad no. pad name x (m) y (m) 30 v1 -672 -2931 31 v0 -496 -2931 32 vcc -320 -2931 33 pa 3 /com4 -112 -2931 34 pa 2 /com3 76 -2931 35 pa 1 /com2 320 -2931 36 pa 0 /com1 544 -2931 37 p5 0 / wkp 0 /seg 1 842 -2931 38 p5 1 / wkp 1 /seg 2 1069 -2931 39 p5 2 / wkp 2 /seg 3 2017 -2931 40 p5 3 / wkp 3 /seg 4 2648 -2931 41 p5 4 / wkp 4 /seg 5 2866 -2484 42 p5 5 / wkp 5 /seg 6 2866 -2296 43 p5 6 / wkp 6 /seg 7 2866 -2061 44 p5 7 / wkp 7 /seg 8 2866 -1846 45 p6 0 /seg 9 2866 -1430 46 p6 1 /seg 10 2866 -1244 47 p6 2 /seg 11 2866 -1056 48 p6 3 /seg 12 2866 -828 49 p6 4 /seg 13 2866 -452 50 p6 5 /seg 14 2866 -264 51 p6 6 /seg 15 2866 -76 52 p6 7 /seg 16 2866 112 53 p7 0 /seg 17 2866 528 54 p7 1 /seg 18 2866 756 55 p7 2 /seg 19 2866 944 56 p7 3 /seg 20 2866 1318 57 p7 4 /seg 21 2866 1506 58 p7 5 /seg 22 2866 1694 59 p7 6 /seg 23 2866 2070 60 p7 7 /seg 24 2866 2367 section 1 overview rev. 6.00 aug 04, 2006 page 14 of 626 rej09b0144-0600 coordinates * pad no. pad name x (m) y (m) 61 p8 0 /seg 25 2866 2931 62 p8 1 /seg 26 2654 2931 63 p8 2 /seg 27 1998 2931 64 p8 3 /seg 28 1803 2931 65 p8 4 /seg 29 /m 1585 2931 66 p8 5 /seg 30 /do 1396 2931 67 p8 6 /seg 31 /cl 2 1209 2931 68 p8 7 /seg 32 /cl 1 977 2931 69 p4 0 /sck 32 631 2931 70 p4 1 /rxd 32 456 2931 71 p4 2 /txd 32 284 2931 72 p4 3 / irq 0 109 2931 73 avcc -64 2931 74 pb 0 /an 0 -236 2931 75 pb 1 /an 1 -409 2931 76 pb 2 /an 2 -581 2931 77 pb 3 /an 3 -925 2931 78 pb 4 /an 4 -1268 2931 79 pb 5 /an 5 -2048 2931 80 pb 6 /an 6 -2658 2931 note: * these values show the coordinates of the centers of pads. the accuracy is 5 m. the home-point position is the chip?s center and the center is located at half the distance between the upper and lower pads and left and right pads. section 1 overview rev. 6.00 aug 04, 2006 page 15 of 626 rej09b0144-0600 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 x y base type code type code (0, 0) : nc pad chip size : 3.55mm 3.45mm voltage level on the back of the chip : gnd figure 1.5 bonding pad location diagram of h8/3827s group (mask rom version) (top view) section 1 overview rev. 6.00 aug 04, 2006 page 16 of 626 rej09b0144-0600 table 1.3 bonding pad coordinates of h8/3827s group (mask rom version) coordinates * pad no. pad name x (m) y (m) 1pb 7 /an 7 -1655 1516 2 avss -1655 1345 3x 1 -1655 999 4x 2 -1655 799 5 vss -1655 536 6osc 2 -1655 334 7osc 1 -1655 226 8 test -1655 37 9 res -1655 -48 10 p1 0 /tmow -1655 -223 11 p1 1 /tmofl -1655 -308 12 p1 2 /tmofh -1655 -393 13 p1 3 /tmig -1655 -563 14 p1 4 / irq 4 / adtrg -1655 -648 15 p1 5 / irq 1 /tmic -1655 -733 16 p1 6 / irq 2 -1655 -818 17 p1 7 / irq 3 /tmif -1655 -988 18 p3 0 /pwm -1655 -1073 19 p3 1 /ud -1655 -1243 20 p3 2 / reso -1655 -1480 21 p3 3 /sck31 -1357 -1605 22 p3 4 /rxd31 -1178 -1605 23 p3 5 /txd31 -1093 -1605 24 p3 6 /aevh -992 -1605 25 p3 7 /aevl -906 -1605 26 vcc -821 -1605 27 vss -736 -1605 28 v3 -651 -1605 29 v2 -566 -1605 section 1 overview rev. 6.00 aug 04, 2006 page 17 of 626 rej09b0144-0600 coordinates * pad no. pad name x (m) y (m) 30 v1 -481 -1605 31 v0 -396 -1605 32 vcc -310 -1605 33 pa 3 /com4 -215 -1605 34 pa 2 /com3 -85 -1605 35 pa 1 /com2 64 -1605 36 pa 0 /com1 197 -1605 37 p5 0 / wkp 0 /seg 1 421 -1605 38 p5 1 / wkp 1 /seg 2 528 -1605 39 p5 2 / wkp 2 /seg 3 957 -1605 40 p5 3 / wkp 3 /seg 4 1154 -1605 41 p5 4 / wkp 4 /seg 5 1655 -1527 42 p5 5 / wkp 5 /seg 6 1655 -1294 43 p5 6 / wkp 6 /seg 7 1655 -1209 44 p5 7 / wkp 7 /seg 8 1655 -1117 45 p6 0 /seg 9 1655 -903 46 p6 1 /seg 10 1655 -796 47 p6 2 /seg 11 1655 -689 48 p6 3 /seg 12 1655 -559 49 p6 4 /seg 13 1655 -345 50 p6 5 /seg 14 1655 -237 51 p6 6 /seg 15 1655 -130 52 p6 7 /seg 16 1655 -23 53 p7 0 /seg 17 1655 191 54 p7 1 /seg 18 1655 317 55 p7 2 /seg 19 1655 424 56 p7 3 /seg 20 1655 639 57 p7 4 /seg 21 1655 746 58 p7 5 /seg 22 1655 853 59 p7 6 /seg 23 1655 1067 60 p7 7 /seg 24 1655 1527 section 1 overview rev. 6.00 aug 04, 2006 page 18 of 626 rej09b0144-0600 coordinates * pad no. pad name x (m) y (m) 61 p8 0 /seg 25 1466 1605 62 p8 1 /seg 26 1230 1605 63 p8 2 /seg 27 1145 1605 64 p8 3 /seg 28 1060 1605 65 p8 4 /seg 29 /m 961 1605 66 p8 5 /seg 30 /do 854 1605 67 p8 6 /seg 31 /cl 2 747 1605 68 p8 7 /seg 32 /cl 1 640 1605 69 p4 0 /slk 32 524 1605 70 p4 1 /rxd 32 439 1605 71 p4 2 /txd 32 354 1605 72 p4 3 / irq 0 269 1605 73 avcc 101 1605 74 pb 0 /an 0 16 1605 75 pb 1 /an 1 -92 1605 76 pb 2 /an 2 -207 1605 77 pb 3 /an 3 -431 1605 78 pb 4 /an 4 -655 1605 79 pb 5 /an 5 -1103 1605 80 pb 6 /an 6 -1290 1605 note: * these values show the coordinates of the centers of pads. the accuracy is 5 m. the home-point position is the chip?s center and the center is located at half the distance between the upper and lower pads and left and right pads. section 1 overview rev. 6.00 aug 04, 2006 page 19 of 626 rej09b0144-0600 x y (0, 0) 80 81 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 41 40 type code 1 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 18 20 21 : nc pad chip size : 4.35mm figure 1.6 bonding pad location diagram of hcd64f38327 and hcd64f38427 (top view) section 1 overview rev. 6.00 aug 04, 2006 page 20 of 626 rej09b0144-0600 table 1.4 bonding pad coordinates of hcd64f38327 and hcd64f38427 coordinates * pad no. pad name x (m) y (m) 1pb 7 /an 7 -2056 1943 2 avss -2056 1656 3x 1 -2056 1570 4x 2 -2056 1360 5 vss -2056 1158 6 vss -2056 1062 7osc 2 -2056 533 8osc 1 -2056 431 9 test -2056 329 10 res -2056 -66 11 p1 0 /tmow -2056 -244 12 p1 1 /tmofl -2056 -402 13 p1 2 /tmofh -2056 -574 14 p1 3 /tmig -2056 -747 15 p1 4 / irq 4 / adtrg -2056 -919 16 p1 5 / irq 1 /tmic -2056 -1091 17 p1 6 / irq 2 -2056 -1263 18 p1 7 / irq 3 /tmif -2056 -1349 19 p3 0 /pwm -2056 -1521 20 p3 1 /ud/excl -2056 -1607 21 p3 2 -2056 -1779 22 p3 3 /sck 31 -1530 -2295 23 p3 4 /rxd 31 -1382 -2295 24 p3 5 /txd 31 -1280 -2295 25 p3 6 /aevh -1178 -2295 26 p3 7 /aevl -1076 -2295 27 cvcc -896 -2295 28 vss -710 -2295 29 v3 -584 -2295 30 v2 -483 -2295 section 1 overview rev. 6.00 aug 04, 2006 page 21 of 626 rej09b0144-0600 coordinates * pad no. pad name x (m) y (m) 31 v1 -382 -2295 32 v0 -281 -2295 33 vcc -145 -2295 34 pa 3 /com4 51 -2295 35 pa 2 /com3 301 -2295 36 pa 1 /com2 441 -2295 37 pa 0 /com1 604 -2295 38 p5 0 / wkp 0 /seg 1 883 -2295 39 p5 1 / wkp 1 /seg 2 1022 -2295 40 p5 2 / wkp 2 /seg 3 1302 -2295 41 p5 3 / wkp 3 /seg 4 1530 -2295 42 p5 4 / wkp 4 /seg 5 2056 -1955 43 p5 5 / wkp 5 /seg 6 2056 -1830 44 p5 6 / wkp 6 /seg 7 2056 -1651 45 p5 7 / wkp 7 /seg 8 2056 -1481 46 p6 0 /seg 9 2056 -1111 47 p6 1 /seg 10 2056 -879 48 p6 2 /seg 11 2056 -671 49 p6 3 /seg 12 2056 -505 50 p6 4 /seg 13 2056 -255 51 p6 5 /seg 14 2056 -130 52 p6 6 /seg 15 2056 -6 53 p6 7 /seg 16 2056 119 54 p7 0 /seg 17 2056 457 55 p7 1 /seg 18 2056 660 56 p7 2 /seg 19 2056 784 57 p7 3 /seg 20 2056 1034 58 p7 4 /seg 21 2056 1159 59 p7 5 /seg 22 2056 1378 60 p7 6 /seg 23 2056 1627 61 p7 7 /seg 24 2056 1840 section 1 overview rev. 6.00 aug 04, 2006 page 22 of 626 rej09b0144-0600 coordinates * pad no. pad name x (m) y (m) 62 p8 0 /seg 25 1777 2295 63 p8 1 /seg 26 1530 2295 64 p8 2 /seg 27 1302 2295 65 p8 3 /seg 28 1147 2295 66 p8 4 /seg 29 1022 2295 67 p8 5 /seg 30 901 2295 68 p8 6 /seg 31 728 2295 69 p8 7 /seg 32 603 2295 70 p4 0 /sck 32 451 2295 71 p4 1 /rxd 32 350 2295 72 p4 2 /txd 32 175 2295 73 p4 3 / irq 0 73 2295 74 avcc -155 2295 75 pb 0 /an 0 -290 2295 76 pb 1 /an 1 -440 2295 77 pb 2 /an 2 -695 2295 78 pb 3 /an 3 -801 2295 79 pb 4 /an 4 -996 2295 80 pb 5 /an 5 -1419 2295 81 pb 6 /an 6 -1530 2295 note: * these values show the coordinates of the centers of pads. the accuracy is 5 m. the home-point position is the chip?s center and the center is located at half the distance between the upper and lower pads and left and right pads. pad numbers 5, 6, and 28 are power supply (vss) pads and must be connected. they should not be left open. pad number 9 (test) must be connected to the vss position. the device will not operate properly if the pads are not connected as indicated. section 1 overview rev. 6.00 aug 04, 2006 page 23 of 626 rej09b0144-0600 24 25 21 22 23 26 27 28 29 30 31 32 36 37 33 34 35 38 39 40 42 43 44 45 48 49 61 63 68 66 47 46 51 64 65 67 62 52 50 41 1 2 3 4 5 6 7 8 9 16 13 14 15 17 12 11 10 19 20 18 59 57 55 58 56 54 53 60 72 73 70 71 69 75 74 77 76 79 78 80 type code x y (0, 0) chip size : 3.45mm figure 1.7 bonding pad location diagram of h8/38327 group (mask rom version) and h8/38427 group (mask rom version) (top view) section 1 overview rev. 6.00 aug 04, 2006 page 24 of 626 rej09b0144-0600 table 1.5 bonding pad coordinates of h8/38327 group (mask rom version) and h8/38427 group (mask rom version) coordinates * pad no. pad name x (m) y (m) 1pb 7 /an 7 -1605 1227 2 avss -1605 1057 3x 1 -1605 941 4x 2 -1605 843 5 vss -1605 619 6osc 2 -1605 503 7osc 1 -1605 405 8 test -1605 299 9 res -1605 201 10 p1 0 /tmow -1605 -185 11 p1 1 /tmofl -1605 -283 12 p1 2 /tmofh -1605 -382 13 p1 3 /tmig -1605 -480 14 p1 4 / irq 4 / adtrg -1605 -578 15 p1 5 / irq 1 /tmic -1605 -676 16 p1 6 / irq 2 -1605 -775 17 p1 7 / irq 3 /tmif -1605 -873 18 p3 0 /pwm -1605 -971 19 p3 1 /ud/excl -1605 -1070 20 p3 2 -1605 -1168 21 p3 3 /sck 31 -1262 -1577 22 p3 4 /rxd 31 -1164 -1577 23 p3 5 /txd 31 -1066 -1577 24 p3 6 /aevh -967 -1577 25 p3 7 /aevl -869 -1577 26 cvcc -704 -1577 27 vss -518 -1577 28 v3 -368 -1577 29 v2 -276 -1577 30 v1 -184 -1577 section 1 overview rev. 6.00 aug 04, 2006 page 25 of 626 rej09b0144-0600 coordinates * pad no. pad name x (m) y (m) 31 v0 -67 -1577 32 vcc 109 -1577 33 pa 3 /com4 237 -1577 34 pa 2 /com3 361 -1577 35 pa 1 /com2 486 -1577 36 pa 0 /com1 611 -1577 37 p5 0 / wkp 0 /seg 1 767 -1577 38 p5 1 / wkp 1 /seg 2 892 -1577 39 p5 2 / wkp 2 /seg 3 1017 -1577 40 p5 3 / wkp 3 /seg 4 1141 -1577 41 p5 4 / wkp 4 /seg 5 1605 -1224 42 p5 5 / wkp 5 /seg 6 1605 -1100 43 p5 6 / wkp 6 /seg 7 1605 -975 44 p5 7 / wkp 7 /seg 8 1605 -850 45 p6 0 /seg 9 1605 -723 46 p6 1 /seg 10 1605 -598 47 p6 2 /seg 11 1605 -473 48 p6 3 /seg 12 1605 -349 49 p6 4 /seg 13 1605 -195 50 p6 5 /seg 14 1605 -70 51 p6 6 /seg 15 1605 55 52 p6 7 /seg 16 1605 179 53 p7 0 /seg 17 1605 336 54 p7 1 /seg 18 1605 460 55 p7 2 /seg 19 1605 585 56 p7 3 /seg 20 1605 710 57 p7 4 /seg 21 1605 835 58 p7 5 /seg 22 1605 959 59 p7 6 /seg 23 1605 1084 60 p7 7 /seg 24 1605 1209 61 p8 0 /seg 25 1130 1577 section 1 overview rev. 6.00 aug 04, 2006 page 26 of 626 rej09b0144-0600 coordinates * pad no. pad name x (m) y (m) 62 p8 1 /seg 26 1006 1577 63 p8 2 /seg 27 881 1577 64 p8 3 /seg 28 756 1577 65 p8 4 /seg 29 631 1577 66 p8 5 /seg 30 507 1577 67 p8 6 /seg 31 382 1577 68 p8 7 /seg 32 257 1577 69 p4 0 /sck 32 -4 1577 70 p4 1 /rxd 32 -97 1577 71 p4 2 /txd 32 -196 1577 72 p4 3 / irq 0 -294 1577 73 avcc -470 1577 74 pb 0 /an 0 -598 1577 75 pb 1 /an 1 -704 1577 76 pb 2 /an 2 -810 1577 77 pb 3 /an 3 -916 1577 78 pb 4 /an 4 -1022 1577 79 pb 5 /an 5 -1128 1577 80 pb 6 /an 6 -1233 1577 note: * these values show the coordinates of the centers of pads. the accuracy is 5 m. the home-point position is the chip?s center and the center is located at half the distance between the upper and lower pads and left and right pads. pad numbers 2, 5, and 27 are power supply (v ss ) pads and must be connected. they should not be left open. pad number 8 (test) must be connected to the vss position. the device will not operate properly if the pads are not connected as indicated. section 1 overview rev. 6.00 aug 04, 2006 page 27 of 626 rej09b0144-0600 1.3.2 pin functions table 1.6 outlines the pin functions of this lsi. table 1.6 pin functions pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions power source pins v cc cv cc 32 26 34 28 input power supply: all v cc pins should be connected to the system power supply. see section 14, power supply circuit, for a cv cc pin (v cc pin in the h8/3827s group). v ss 5 27 7 29 input ground: all v ss pins should be connected to the system power supply (0 v). av cc 73 75 input analog power supply: this is the power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. av ss 2 4 input analog ground: this is the a/d converter ground pin. it should be connected to the system power supply (0v). v 0 31 33 output v 1 v 2 v 3 30 29 28 32 31 30 input lcd power supply: these are the power supply pins for the lcd controller/driver. they incorporate a power supply split-resistance, and are normally used with v 0 and v 1 shorted. section 1 overview rev. 6.00 aug 04, 2006 page 28 of 626 rej09b0144-0600 pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions clock pins osc 1 7 9 input osc 2 6 8 output these pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. see section 4, clock pulse generators, for a typical connection diagram. x 1 3 5 input x 2 4 6 output these pins connect to a 32.768-khz or 38.4-khz crystal oscillator. see section 4, clock pulse generators, for a typical connection diagram. excl 19 ? input this pin connects to a 32.768-khz or 38.4-khz external clock. see section 4, clock pulse generators, for typical connection diagram. this function is only available on the h8/38327 group and h8/38427 group. system control res 9 11 input reset: when this pin is driven low, the chip is reset reso 20 22 output reset output: outputs the cpu internal reset signal. this function is not implemented in the h8/38327 group and h8/38427 group. test 8 10 input test pin: this pin is reserved and cannot be used. it should be connected to v ss . interrupt pins irq 0 irq 1 irq 2 irq 3 irq 4 72 15 16 17 14 74 17 18 19 16 input irq interrupt request 0 to 4: these are input pins for edge-sensitive external interrupts, with a selection of rising or falling edge wkp 7 to wkp 0 44 to 37 46 to 39 input wakeup interrupt request 0 to 7: these are input pins for rising or falling- edge-sensitive external interrupts. timer pins tmow 10 12 output clock output: this is an output pin for waveforms generated by the timer a output circuit. aevl aevh 25 24 27 26 input asynchronous event counter event input: this is an event input pin for input to the asynchronous event counter. section 1 overview rev. 6.00 aug 04, 2006 page 29 of 626 rej09b0144-0600 pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions timer pins tmic 15 17 input timer c event input: this is an event input pin for input to the timer c counter. ud 19 21 input timer c up/down select: this pin selects up- or down-counting for the timer c counter. the counter operates as a down-counter when this pin is high, and as an up-counter when low. tmif 17 19 input timer f event input: this is an event input pin for input to the timer f counter. tmofl 11 13 output timer fl output: this is an output pin for waveforms generated by the timer fl output compare function. tmofh 12 14 output timer fh output: this is an output pin for waveforms generated by the timer fh output compare function. tmig 13 15 input timer g capture input: this is an input pin for timer g input capture. 14-bit pwm pin pwm 18 20 output 14-bit pwm output: this is an output pin for waveforms generated by the 14- bit pwm i/o ports pb 7 to pb 0 1, 80 to 74 3 to 1, 80 to 76 input port b: this is an 8-bit input port. p4 3 72 74 input port 4 (bit 3): this is a 1-bit input port. p4 2 to p4 0 71 to 69 73 to 71 i/o port 4 (bits 2 to 0): this is a 3-bit i/o port. input or output can be designated for each bit by means of port control register 4 (pcr4). pa 3 to pa 0 33 to 36 35 to 38 i/o port a: this is a 4-bit i/o port. input or output can be designated for each bit by means of port control register a (pcra). p1 7 to p1 0 17 to 10 19 to 12 i/o port 1: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 1 (pcr1). section 1 overview rev. 6.00 aug 04, 2006 page 30 of 626 rej09b0144-0600 pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions i/o ports p3 7 to p3 0 25 to 18 27 to 20 i/o port 3: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 3 (pcr3). when the on-chip emulator is used, pin p3 2 is reserved for use exclusively by the emulator and therefore cannot be accessed by the user. with the f-ztat version, pull up pin p3 2 to high level to cancel a reset in the in the user mode. p5 7 to p5 0 44 to 37 46 to 39 i/o port 5: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 5 (pcr5). p6 7 to p6 0 52 to 45 54 to 47 i/o port 6: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 6 (pcr6). p7 7 to p7 0 60 to 53 62 to 55 i/o port 7: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 7 (pcr7). p8 7 to p8 0 68 to 61 70 to 63 i/o port 8: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 8 (pcr8). when the on-chip emulator is used, pins p8 5 , p8 6 , and p8 7 are reserved for use exclusively by the emulator and therefore cannot be accessed by the user. rxd 31 22 24 input sci3-1 receive data input: this is the sci31 data input pin. txd 31 23 25 output sci3-1 transmit data output: this is the sci31 data output pin. serial communi- cation interface (sci) sck 31 21 23 i/o sci3-1 clock i/o: this is the sci31 clock i/o pin. rxd 32 70 72 input sci3-2 receive data input: this is the sci32 data input pin. txd 32 71 73 output sci3-2 transmit data output: this is the sci32 data output pin. sck 32 69 71 i/o sci3-2 clock i/o: this is the sci32 clock i/o pin. section 1 overview rev. 6.00 aug 04, 2006 page 31 of 626 rej09b0144-0600 pin no. type symbol fp-80a tfp-80c fp-80b i/o name and functions a/d converter an7 to an0 1 80 to 74 3 to 1 80 to 76 input analog input channels 7 to 0: these are analog data input channels to the a/d converter adtrg 14 16 input a/d converter trigger input: this is the external trigger input pin to the a/d converter com 4 to com 1 33 to 36 35 to 38 output lcd common output: these are the lcd common output pins. lcd controller/ driver seg 32 to seg 1 68 to 37 70 to 39 output lcd segment output: these are the lcd segment output pins. cl 1 68 70 output lcd latch clock: this is the output pin for the segment external expansion display data latch clock. this function is not implemented in the h8/38327 group and h8/38427 group. cl 2 67 69 output lcd shift clock: this is the output pin for the segment external expansion display data shift clock. this function is not implemented in the h8/38327 group and h8/38427 group. do 66 68 output lcd serial data output: this is the output pin for segment external expansion serial display data. this function is not implemented in the h8/38327 group and h8/38427 group. m 65 67 output lcd alternation signal: this is the output pin for the segment external expansion lcd alternation signal. this function is not implemented in the h8/38327 group and h8/38427 group. section 1 overview rev. 6.00 aug 04, 2006 page 32 of 626 rej09b0144-0600 section 2 cpu rev. 6.00 aug 04, 2006 page 33 of 626 rej09b0144-0600 section 2 cpu 2.1 overview the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise instruction set is designed for high-speed operation. 2.1.1 features features of the h8/300l cpu are listed below. ? general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers ? instruction set with 55 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct ? register indirect ? register indirect with displacement ? register indirect with post-increment or pre-decrement ? absolute address ? immediate ? program-counter relative ? memory indirect ? 64-kbyte address space ? high-speed operation ? all frequently used instructions are executed in two to four states ? high-speed arithmetic and logic operations ? 8- or 16-bit register-register add or subtract: 0.25 s * ? 8 8-bit multiply: 1.75 s * ? 16 8-bit divide: 1.75 s * note: * these values are at = 8 mhz. ? low-power operation modes sleep instruction for transfer to low-power operation section 2 cpu rev. 6.00 aug 04, 2006 page 34 of 626 rej09b0144-0600 2.1.2 address space the h8/300l cpu supports an address space of up to 64 kbytes for storing program code and data. see section 2.8, memory map, for details of the memory map. 2.1.3 register configuration figure 2.1 shows the register structure of the h8/300l cpu. there are two groups of registers: the general registers and control registers. 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers (cr) 753210 64 figure 2.1 cpu registers section 2 cpu rev. 6.00 aug 04, 2006 page 35 of 626 rej09b0144-0600 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception processing and subroutine calls. when it functions as the stack pointer, as indicated in figure 2.2, sp (r7) points to the top of the stack. lower address side [h'0000] upper address side [h'ffff] unused area stack area sp (r7) figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). program counter (pc) this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0). section 2 cpu rev. 6.00 aug 04, 2006 page 36 of 626 rej09b0144-0600 condition code register (ccr) this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. these bits can be read and written by software (using the ldc, stc, andc, orc, and xorc instructions). the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions. bit 7?interrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see section 3.3, interrupts. bit 6?user bit (u): can be used freely by the user. bit 5?half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4?user bit (u): can be used freely by the user. bit 3?negative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2?zero flag (z): set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. bit 1?overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. section 2 cpu rev. 6.00 aug 04, 2006 page 37 of 626 rej09b0144-0600 refer to the h8/300l series programming manual for the action of each instruction on the flag bits. 2.2.3 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. ? bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). ? all arithmetic and logic instructions except adds and subs can operate on byte data. ? the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions operate on word data. ? the daa and das instructions perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. section 2 cpu rev. 6.00 aug 04, 2006 page 38 of 626 rej09b0144-0600 2.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2.3. 7 6 5 4 3 2 1 0 don?t care data type register no. data format 70 1-bit data rnh 76543210 don?t care 70 1-bit data rnl msb lsb don?t care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl legend: rnh: rnl: msb: lsb: upper byte of general register lower byte of general register most significant bit least significant bit msb lsb don?t care 70 msb lsb 15 0 upper digit lower digit don?t care 70 3 4 don?t care upper digit lower digit 70 3 4 figure 2.3 register data formats section 2 cpu rev. 6.00 aug 04, 2006 page 39 of 626 rej09b0144-0600 2.3.2 memory data formats figure 2.4 indicates the data formats in memory. the h8/300l cpu can access word data stored in memory (mov.w instruction), but the word data must always begin at an even address. if word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. the same applies to instruction codes. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack ccr: condition code register note: ignored on return * figure 2.4 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored. section 2 cpu rev. 6.00 aug 04, 2006 page 40 of 626 rej09b0144-0600 2.4 addressing modes 2.4.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2.1. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment register indirect with pre-decrement @rn+ @?rn 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register direct?rn: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. 2. register indirect?@rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. register indirect with displacement?@(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even. section 2 cpu rev. 6.00 aug 04, 2006 page 41 of 626 rej09b0144-0600 4. register indirect with post-increment or pre-decrement?@rn+ or @?rn: ? register indirect with post-increment?@rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. ? register indirect with pre-decrement?@?rn the @?rn mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address?@aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate?#xx:8 or #xx:16: the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative?@(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is ?126 to +128 bytes (?63 to +64 words) from the current address. the displacement should be an even number. 8. memory indirect?@@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. section 2 cpu rev. 6.00 aug 04, 2006 page 42 of 626 rej09b0144-0600 the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/300l series, the lower end of the address area is also used as a vector area. see section 3.3, interrupts, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see section 2.3.2, memory data formats, for further information. 2.4.2 effective address calculation table 2.2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify the operand. register indirect (1) (bset, bclr, bnot, and btst instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in the operand. section 2 cpu rev. 6.00 aug 04, 2006 page 43 of 626 rej09b0144-0600 table 2.2 effective address calculation addressing mode and instruction format op rm 76 3 40 15 no. effective address calculation method effective address (ea) 1 register direct, rn operand is contents of registers indicated by rm/rn register indirect, @rn contents (16 bits) of register indicated by rm 0 15 register indirect with displacement, @(d:16, rn) op rm rn 87 3 40 15 op rm 76 3 40 15 disp op rm 76 3 40 15 register indirect with post-increment, @rn+ op rm 76 3 40 15 register indirect with pre-decrement, @ ? rn 2 3 4 incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 rm 30 rn 30 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm section 2 cpu rev. 6.00 aug 04, 2006 page 44 of 626 rej09b0144-0600 addressing mode and instruction format no. effective address calculation method effective address (ea) 5 absolute address @aa:8 operand is 1- or 2-byte immediate data @aa:16 op 87 0 15 op 0 15 imm op disp 70 15 program-counter relative @(d:8, pc) 6 7 0 15 pc contents 0 15 0 15 abs h'ff 87 0 15 0 15 abs op #xx:16 op 87 0 15 imm immediate #xx:8 8 sign extension disp section 2 cpu rev. 6.00 aug 04, 2006 page 45 of 626 rej09b0144-0600 addressing mode and instruction format no. effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 legend: rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address abs section 2 cpu rev. 6.00 aug 04, 2006 page 46 of 626 rej09b0144-0600 2.5 instruction set the h8/300l series can use a total of 55 instructions, which are grouped by function in table 2.3. table 2.3 instruction set function instructions number data transfer mov, push * 1 , pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @?sp. pop rn is equivalent to mov.w @sp+, rn. the same applies to the machine language. 2. bcc is a conditional branch instruction in which cc represents a condition code. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. section 2 cpu rev. 6.00 aug 04, 2006 page 47 of 626 rej09b0144-0600 notation rd general register (destination) rs general register (source) rn general register (ead), section 2 cpu rev. 6.00 aug 04, 2006 page 48 of 626 rej09b0144-0600 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:16, @?rn, and @rn+ addressing modes are available for word data. the @aa:8 addressing mode is available for byte data only. the @?r7 and @r7+ modes require word operands. do not specify byte size for these two modes. pop w @sp+ rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. push w rn @?sp pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @?sp. note: * size: operand size b: byte w: word certain precautions are required in data access. see section 2.9.1, notes on data access, for details. section 2 cpu rev. 6.00 aug 04, 2006 page 49 of 626 rej09b0144-0600 15 0 87 op rm rn mov rm ? rm 15 0 87 op rn abs @aa:8 ? sp figure 2.5 data transfer instruction codes section 2 cpu rev. 6.00 aug 04, 2006 page 50 of 626 rej09b0144-0600 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. table 2.5 arithmetic instructions instruction size * function add sub b/w rd rs rd, rd + #imm rd performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc dec b rd 1 rd increments or decrements a general register by 1. adds subs w rd 1 rd, rd 2 rd adds or subtracts 1 or 2 to or from a general register daa das b rd decimal adjust rd decimal-adjusts (adjusts to 4-bit bcd) an addition or subtraction result in a general register by referring to the ccr mulxu b rd rs rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result divxu b rd rs rd performs 16-bit 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder cmp b/w rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and indicates the result in the ccr. word data can be compared only between two general registers. neg b 0 ? rd rd obtains the two?s complement (arithmetic complement) of data in a general register note: * size: operand size b: byte w: word section 2 cpu rev. 6.00 aug 04, 2006 page 51 of 626 rej09b0144-0600 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. table 2.6 logic operation instructions instruction size * function and b rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data or b rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data xor b rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data not b ~ rd rd obtains the one?s complement (logical complement) of general register contents note: * size: operand size b: byte section 2 cpu rev. 6.00 aug 04, 2006 page 52 of 626 rej09b0144-0600 2.5.4 shift operations table 2.7 describes the eight shift instructions. table 2.7 shift instructions instruction size * function shal shar b rd shift rd performs an arithmetic shift operation on general register contents shll shlr b rd shift rd performs a logical shift operation on general register contents rotl rotr b rd rotate rd rotates general register contents rotxl rotxr b rd rotate through carry rd rotates general register contents through the c (carry) bit note: * size: operand size b: byte section 2 cpu rev. 6.00 aug 04, 2006 page 53 of 626 rej09b0144-0600 figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) legend: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op figure 2.6 arithmetic, logic, and shift instruction codes section 2 cpu rev. 6.00 aug 04, 2006 page 54 of 626 rej09b0144-0600 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b 1 ( section 2 cpu rev. 6.00 aug 04, 2006 page 55 of 626 rej09b0144-0600 instruction size * function bxor b c ( section 2 cpu rev. 6.00 aug 04, 2006 page 56 of 626 rej09b0144-0600 15 0 87 op imm rn operand: bit no.: legend: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes section 2 cpu rev. 6.00 aug 04, 2006 page 57 of 626 rej09b0144-0600 legend: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes (cont) section 2 cpu rev. 6.00 aug 04, 2006 page 58 of 626 rej09b0144-0600 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function bcc ? branches to the designated address if condition cc is true. the branching conditions are given below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address bsr ? branches to a subroutine at a specified address jsr ? branches to a subroutine at a specified address rts ? returns from a subroutine section 2 cpu rev. 6.00 aug 04, 2006 page 59 of 626 rej09b0144-0600 legend: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts figure 2.8 branching instruction codes section 2 cpu rev. 6.00 aug 04, 2006 page 60 of 626 rej09b0144-0600 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size * function rte ? returns from an exception-handling routine sleep ? causes a transition from active mode to a power-down mode. see section 5, power-down modes, for details. ldc b rs ccr, #imm ccr moves immediate data or general register contents to the condition code register stc b ccr rd copies the condition code register to a specified general register andc b ccr #imm ccr logically ands the condition code register with immediate data orc b ccr #imm ccr logically ors the condition code register with immediate data xorc b ccr #imm ccr logically exclusive-ors the condition code register with immediate data nop ? pc + 2 pc only increments the program counter note: * size: operand size b: byte section 2 cpu rev. 6.00 aug 04, 2006 page 61 of 626 rej09b0144-0600 legend: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) figure 2.9 system control instruction codes section 2 cpu rev. 6.00 aug 04, 2006 page 62 of 626 rej09b0144-0600 2.5.8 block data transfer instruction table 2.11 describes the block data transfer instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction instruction size function eepmov ? if r4l 0 then repeat @r5+ @r6+ r4l ?1 r4l until r4l = 0 else next; block transfer instruction. transfers the number of data bytes specified by r4l from locations starting at the address indicated by r5 to locations starting at the address indicated by r6. after the transfer, the next instruction is executed. certain precautions are required in using the eepmov instruction. see section 2.9.3, notes on use of the eepmov instruction, for details. legend: op: operation field 15 0 87 op op figure 2.10 block data transfer instruction code section 2 cpu rev. 6.00 aug 04, 2006 page 63 of 626 rej09b0144-0600 2.6 basic operational timing cpu operation is synchronized by a system clock ( ) or a subclock ( sub ). for details on these clock signals see section 4, clock pulse generators. the period from a rising edge of or sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.11 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub figure 2.11 on-chip memory access cycle section 2 cpu rev. 6.00 aug 04, 2006 page 64 of 626 rej09b0144-0600 2.6.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits, so access is by byte size only. this means that for accessing word data, two instructions must be used. figures 2.12 and 2.13 show the on-chip peripheral module access cycle. two-state access to on-chip peripheral modules t 1 state bus cycle t 2 state figure 2.12 on-chip peripheral module access cycle (2-state access) section 2 cpu rev. 6.00 aug 04, 2006 page 65 of 626 rej09b0144-0600 three-state access to on-chip peripheral modules t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub figure 2.13 on-chip peripheral module access cycle (3-state access) 2.7 cpu states 2.7.1 overview there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode and subactive mode. in the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. these states are shown in figure 2.14. figure 2.15 shows the state transitions. section 2 cpu rev. 6.00 aug 04, 2006 page 66 of 626 rej09b0144-0600 cpu state reset state program execution state program halt state exception- handling state active (high speed) mode active (medium speed) mode subactive mode sleep (high-speed) mode standby mode watch mode subsleep mode low-power modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized note: see section 5, power-down modes, for details on the modes and their transitions. sleep (medium-speed) mode figure 2.14 cpu operation states section 2 cpu rev. 6.00 aug 04, 2006 page 67 of 626 rej09b0144-0600 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source occurs reset occurs interrupt source occurs exception- handling complete reset occurs figure 2.15 state transitions 2.7.2 program execution state in the program execution state the cpu executes program instructions in sequence. there are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. see section 5, power-down modes for details on these modes. 2.7.3 program halt state in the program halt state there are five modes: two sleep modes (high speed and medium speed), standby mode, watch mode, and subsleep mode. see section 5, power-down modes for details on these modes. 2.7.4 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see section 3.3, interrupts. section 2 cpu rev. 6.00 aug 04, 2006 page 68 of 626 rej09b0144-0600 2.8 memory map 2.8.1 memory map the memory map of the h8/3822r, h8/38322, and h8/38422 is shown in figure 2.16 (1), that of the h8/3823r, h8/38323, and h8/38423 in figure 2.16 (2), that of the h8/3824r, h8/3824s, h8/38324, and h8/38424 in figure 2.16 (3), that of the h8/3825r, h8/3825s, h8/38325, and h8/38425 in figure 2.16 (4), that of the h8/3826r, h8/3826s, h8/38326, and h8/38426 in figure 2.16 (5), and that of the h8/3827r, h8/3827s, h8/38327, and h8/38427 in figure 2.16 (6). h'0000 h'0029 h'002a h'3fff h'f740 h'f75f h'f780 h'fb7f h'ff90 h'ffff interrupt vector area on-chip rom 16 kbytes (16384 bytes) 1024 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (1) h8/3822r, h8/38322, and h8/38422 memory map section 2 cpu rev. 6.00 aug 04, 2006 page 69 of 626 rej09b0144-0600 h'0000 h'0029 h'002a h'5fff h'f740 h'f75f h'f780 h'fb7f h'ff90 h'ffff interrupt vector area on-chip rom 24 kbytes (24576 bytes) 1024 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (2) h8/3823r, h8/38323, and h8/38423 memory map section 2 cpu rev. 6.00 aug 04, 2006 page 70 of 626 rej09b0144-0600 interrupt vector area h'0000 h'7fff h'e000 h'f300 h'f6ff h'f780 h'ff7f h'efff h'0029 h'002a h'f020 h'f02b h'f740 h'f75f h'ff90 h'ffff hd64f38324 hd64f38424 (flash memory version) on-chip rom 32 kbytes (32768 bytes) 2048 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used not used not used not used lcd ram (32 bytes) notes: 1. not accessible by the user when the on-chip emulator is used. 2. a programming control program is used to program flash memory. do not use a user program to perform programming when the on-chip emulator is used. this area is not used in the mask rom version. firmware for on-chip emulator * 1 internal i/o registers (work area for programming flash memory: 1 kbyte) * 2 interrupt vector area h'0000 h'7fff h'f780 h'ff7f h'0029 h'002a h'f740 h'f75f h'ff90 h'ffff hd6433824r (mask rom version) HD6433824S (mask rom version) hd64338324 (mask rom version) hd64338424 (mask rom version) on-chip rom 32 kbytes (32768 bytes) 2048 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (3) h8/3824r, h8/3824s, h8/38324, and h8/38424 memory map section 2 cpu rev. 6.00 aug 04, 2006 page 71 of 626 rej09b0144-0600 h'0000 h'0029 h'002a h'9fff h'f740 h'f75f h'f780 h'ff7f h'ff90 h'ffff interrupt vector area on-chip rom 40 kbytes (40960 bytes) 2048 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (4) h8/3825r, h8/3825s, h8/38325, and h8/38425 memory map section 2 cpu rev. 6.00 aug 04, 2006 page 72 of 626 rej09b0144-0600 h'0000 h'0029 h'002a h'bfff h'f740 h'f75f h'f780 h'ff7f h'ff90 h'ffff interrupt vector area on-chip rom 48 kbytes (49152 bytes) 2048 bytes on-chip ram not used internal i/o registers (112 bytes) not used not used lcd ram (32 bytes) figure 2.16 (5) h8/3826r, h8/3826s, h8/38326, and h8/38426 memory map section 2 cpu rev. 6.00 aug 04, 2006 page 73 of 626 rej09b0144-0600 interrupt vector area h'0000 h'e000 h'f300 h'f6ff h'f780 h'ff7f h'efff h'0029 h'002a h'f020 h'f02b h'f740 h'f75f h'ff90 h'ffff hd64f38327 (flash memory version) hd64f38427 (flash memory version) on-chip rom 61440 bytes 2048 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used not used not used lcd ram (32 bytes) notes: 1. not accessible by the user when the on-chip emulator is used. 2. a programming control program is used to program flash memory. do not use a user program to perform programming when the on-chip emulator is used. this area is not used in the mask rom version. firmware for on-chip emulator * 1 internal i/o registers (work area for programming flash memory: 1 kbyte) * 2 interrupt vector area h'0000 h'edff h'f780 h'ff7f h'0029 h'002a h'f740 h'f75f h'ff90 h'ffff hd6433827r (mask rom version) hd6433827s (mask rom version) hd64338327 (mask rom version) hd64338427 (mask rom version) hd6473827r (prom version) on-chip rom 60928 bytes 2048 bytes on-chip ram internal i/o registers (112 bytes) not used not used not used lcd ram (32 bytes) figure 2.16 (6) h8/3827r, h8/3827s, h8/38327, and h8/38427 memory map section 2 cpu rev. 6.00 aug 04, 2006 page 74 of 626 rej09b0144-0600 2.9 application notes 2.9.1 notes on data access 1. access to empty areas: the address space of the h8/300l cpu includes empty areas in addition to the ram, registers, and rom areas available to the user. if these empty areas are mistakenly accessed by an application program, the following results will occur. data transfer from cpu to empty area: the transferred data will be lost. this action may also cause the cpu to misoperate. data transfer from empty area to cpu: unpredictable data is transferred. 2. access to internal i/o registers: internal data transfer to or from on-chip modules other than the rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area: upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu: upper byte: will be written to upper part of cpu register. lower byte: unpredictable data will be written to lower part of cpu register. byte size instructions should therefore be used when transferring data to or from i/o registers other than the on-chip rom and ram areas. figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed. section 2 cpu rev. 6.00 aug 04, 2006 page 75 of 626 rej09b0144-0600 interrupt vector area (42 bytes) on-chip rom 32kbytes * 1 on-chip ram not used not used not used lcd ram (32 bytes) internal i/o registers (112 bytes) access word byte 2 ??? ??? 2 ??? 2 figure 2.17 data size and number of states for access to and from on-chip peripheral modules section 2 cpu rev. 6.00 aug 04, 2006 page 76 of 626 rej09b0144-0600 2.9.2 notes on bit manipulation the bset, bclr, bnot, bst, and bist instructions read one byte of data, modify the data, then write the data byte again. special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an i/o port. order of operation operation 1 read read byte data at the designated address 2 modify modify a designated bit in the read data 3 write write the altered byte data to the designated address 1. bit manipulation in two registers assigned to the same address example 1: timer load register and timer counter figure 2.18 shows an example in which two timer registers share the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. order of operation operation 1 read timer counter data is read (one byte) 2 modify the cpu modifies (sets or resets) the bit designated in the instruction 3 write the altered byte data is written to the timer load register the timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. read write count clock timer counter timer load register reload internal bus figure 2.18 timer configuration example section 2 cpu rev. 6.00 aug 04, 2006 page 77 of 626 rej09b0144-0600 example 2: bset instruction executed designating port 3 p3 7 and p3 6 are designated as input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins and output low-level signals. in this example, the bset instruction is used to change pin p3 0 to high-level output. [a: prior to executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr300111111 pdr310000000 [b: bset instruction executed] bset #0 , @pdr3 the bset instruction is executed designating port 3. [c: after executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr300111111 pdr301000001 [d: explanation of how bset operates] when the bset instruction is executed, first the cpu reads port 3. since p3 7 and p3 6 are input pins, the cpu reads the pin states (low-level and high-level input). p3 5 to p3 0 are output pins, so the cpu reads the value in pdr3. in this example pdr3 has a value of h'80, but the value read by the cpu is h'40. next, the cpu sets bit 0 of the read data to 1, changing the pdr3 data to h'41. finally, the cpu writes this value (h'41) to pdr3, completing execution of bset. as a result of this operation, bit 0 in pdr3 becomes 1, and p3 0 outputs a high-level signal. however, bits 7 and 6 of pdr3 end up with different values. section 2 cpu rev. 6.00 aug 04, 2006 page 78 of 626 rej09b0144-0600 to avoid this problem, store a copy of the pdr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr3. [a: prior to executing bset] mov. b #h'80, r0l mov. b r0l, @ram0 mov. b r0l, @pdr3 the pdr3 value (h'80) is written to a work area in memory (ram0) as well as to pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr300111111 pdr310000000 ram010000000 [b: bset instruction executed] bset #0 , @ram0 the bset instruction is executed designating the pdr3 work area (ram0). [c: after executing bset] mov. b @ram0, r0l the work area (ram0) value is written to pdr3. mov. b r0l, @pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr300111111 pdr310000001 ram010000001 section 2 cpu rev. 6.00 aug 04, 2006 page 79 of 626 rej09b0144-0600 2. bit manipulation in a register containing a write-only bit example 3: bclr instruction executed designating port 3 control register pcr3 as in the examples above, p3 7 and p3 6 are input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins that output low-level signals. in this example, the bclr instruction is used to change pin p3 0 to an input port. it is assumed that a high-level signal will be input to this input pin. [a: prior to executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr300111111 pdr310000000 [b: bclr instruction executed] bclr #0 , @pcr3 the bclr instruction is executed designating pcr3. [c: after executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output output output output output output output output input pin state low level high level low level low level low level low level low level high level pcr311111110 pdr310000000 [d: explanation of how bclr operates] when the bclr instruction is executed, first the cpu reads pcr3. since pcr3 is a write-only register, the cpu reads a value of h'ff, even though the pcr3 value is actually h'3f. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, this value (h'fe) is written to pcr3 and bclr instruction execution ends. as a result of this operation, bit 0 in pcr3 becomes 0, making p3 0 an input port. however, bits 7 and 6 in pcr3 change to 1, so that p3 7 and p3 6 change from input pins to output pins. section 2 cpu rev. 6.00 aug 04, 2006 page 80 of 626 rej09b0144-0600 to avoid this problem, store a copy of the pcr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pcr3. [a: prior to executing bclr] mov. b #h'3f, r0l the pcr3 value (h'3f) is written to a work area in memory mov. b r0l, @ram0 (ram0) as well as to pcr3. mov. b r0l, @pcr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr300111111 pdr310000000 ram000111111 [b: bclr instruction executed] bclr #0 , @ram0 the bclr instruction is executed designating the pcr3 work area (ram0). [c: after executing bclr] mov. b @ram0, r0l the work area (ram0) value is written to pcr3. mov. b r0l, @pcr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr300111110 pdr310000000 ram000111110 section 2 cpu rev. 6.00 aug 04, 2006 page 81 of 626 rej09b0144-0600 table 2.12 lists the pairs of registers that share identical addresses. table 2.13 lists the registers that contain write-only bits. table 2.12 registers with shared addresses register name abbr. address timer counter and timer load register c tcc/tlc h'ffb5 port data register 1 * pdr1 h'ffd4 port data register 3 * pdr3 h'ffd6 port data register 4 * pdr4 h'ffd7 port data register 5 * pdr5 h'ffd8 port data register 6 * pdr6 h'ffd9 port data register 7 * pdr7 h'ffda port data register 8 * pdr8 h'ffdb port data register a * pdra h'ffdd note: * port data registers have the same addresses as input pins. table 2.13 registers with write-only bits register name abbr. address port control register 1 pcr1 h'ffe4 port control register 3 pcr3 h'ffe6 port control register 4 pcr4 h'ffe7 port control register 5 pcr5 h'ffe8 port control register 6 pcr6 h'ffe9 port control register 7 pcr7 h'ffea port control register 8 pcr8 h'ffeb port control register a pcra h'ffed timer control register f tcrf h'ffb6 pwm control register pwcr h'ffd0 pwm data register u pwdru h'ffd1 pwm data register l pwdrl h'ffd2 section 2 cpu rev. 6.00 aug 04, 2006 page 82 of 626 rej09b0144-0600 2.9.3 notes on use of the eepmov instruction ? the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. ? when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. h'ffff not allowed section 3 exception handling rev. 6.00 aug 04, 2006 page 83 of 626 rej09b0144-0600 section 3 exception handling 3.1 overview exception handling is performed in this lsi when a reset or interrupt occurs. table 3.1 shows the priorities of these two types of exception handling. table 3.1 exception handling types and priorities priority exception source time of start of exception handling high reset exception handling starts as soon as the reset state is cleared low interrupt when an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 reset 3.2.1 overview a reset is the highest-priority exception. the internal state of the cpu and the registers of the on- chip peripheral modules are initialized. 3.2.2 reset sequence as soon as the res pin goes low, all processing is stopped and the chip enters the reset state. to make sure the chip is reset properly, observe the following precautions. ? at power on: hold the res pin low until the clock pulse generator output stabilizes. ? resetting during operation: hold the res pin low for at least 10 system clock cycles. reset exception handling takes place as follows. ? the cpu internal state and the registers of on-chip peripheral modules are initialized, with the i bit of the condition code register (ccr) set to 1. ? the pc is loaded from the reset exception handling vector address (h'0000 to h'0001), after which the program starts executing from the address indicated in pc. section 3 exception handling rev. 6.00 aug 04, 2006 page 84 of 626 rej09b0144-0600 when system power is turned on or off, the res pin should be held low. figure 3.1 shows the reset sequence starting from res input. vector fetch internal address bus internal read signal internal write signal internal data bus (16-bit) res internal processing program initial instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) first instruction of program (2) (3) (2) (1) reset cleared figure 3.1 reset sequence 3.2.3 interrupt immediately after reset after a reset, if an interrupt were to be accepted before the stack pointer (sp: r7) was initialized, pc and ccr would not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling all interrupts are masked. for this reason, the initial program instruction is always executed immediately after a reset. this instruction should initialize the stack pointer (e.g. mov.w #xx: 16, sp). section 3 exception handling rev. 6.00 aug 04, 2006 page 85 of 626 rej09b0144-0600 3.3 interrupts 3.3.1 overview the interrupt sources include 13 external interrupts (irq 4 to irq 0 , wkp 7 to wkp 0 ) and 23 internal interrupts from on-chip peripheral modules. table 3.2 shows the interrupt sources, their priorities, and their vector addresses. when more than one interrupt is requested, the interrupt with the highest priority is processed. the interrupts have the following features: ? internal and external interrupts can be masked by the i bit in ccr. when the i bit is set to 1, interrupt request flags can be set but the interrupts are not accepted. ? irq 4 to irq 0 and wkp 7 to wkp 0 can be set to either rising edge sensing or falling edge sensing. section 3 exception handling rev. 6.00 aug 04, 2006 page 86 of 626 rej09b0144-0600 table 3.2 interrupt sources and their priorities interrupt source interrupt vector number vector address priority res watchdog timer reset 0 h'0000 to h'0001 high irq 0 irq 0 4 h'0008 to h'0009 irq 1 irq 1 5 h'000a to h'000b irq 2 irq 2 6 h'000c to h'000d irq 3 irq 3 7 h'000e to h'000f irq 4 irq 4 8 h'0010 to h'0011 wkp 0 wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 wkp 0 wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 9 h'0012 to h'0013 timer a timer a overflow 11 h'0016 to h'0017 asynchronous counter asynchronous counter overflow 12 h'0018 to h'0019 timer c timer c overflow or underflow 13 h'001a to h'001b timer fl timer fl compare match timer fl overflow 14 h'001c to h'001d timer fh timer fh compare match timer fh overflow 15 h'001e to h'001f timer g timer g input capture timer g overflow 16 h'0020 to h'0021 sci3-1 sci3-1 transmit end sci3-1 transmit data empty sci3-1 receive data full sci3-1 overrrun error sci3-1 framing error sci3-1 parity error 17 h'0022 to h'0023 sci3-2 sci3-2 transmit end sci3-2 transmit data empty sci3-2 receive data full sci3-2 overrun error sci3-2 framing error sci3-2 parity error 18 h'0024 to h'0025 a/d a/d conversion end 19 h'0026 to h'0027 (sleep instruction executed) direct transfer 20 h'0028 to h'0029 low note: vector addresses h'0002 to h'0007 and h'0014 to h'0015 are reserved and cannot be used. section 3 exception handling rev. 6.00 aug 04, 2006 page 87 of 626 rej09b0144-0600 3.3.2 interrupt control registers table 3.3 lists the registers that control interrupts. table 3.3 interrupt control registers name abbreviation r/w initial value address irq edge select register iegr r/w h'e0 h'fff2 interrupt enable register 1 ienr1 r/w h'00 h'fff3 interrupt enable register 2 ienr2 r/w h'00 h'fff4 interrupt request register 1 irr1 r/w * h'20 h'fff6 interrupt request register 2 irr2 r/w * h'00 h'fff7 wakeup interrupt request register iwpr r/w * h'00 h'fff9 wakeup edge select register wegr r/w h'00 h'ff90 note: * write is enabled only for writing of 0 to clear a flag. 1. irq edge select register (iegr) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ieg4 0 r/w 3 ieg3 0 r/w 0 ieg0 0 r/w 2 ieg2 0 r/w 1 ieg1 0 r/w iegr is an 8-bit read/write register used to designate whether pins irq 4 to irq 0 are set to rising edge sensing or falling edge sensing. bits 7 to 5: reserved bits bits 7 to 5 are reserved: they are always read as 1 and cannot be modified. bit 4: irq 4 edge select (ieg4) bit 4 selects the input sensing of the irq 4 pin and adtrg pin. bit 4 ieg4 description 0 falling edge of irq 4 and adtrg pin input is detected (initial value) 1 rising edge of irq 4 and adtrg pin input is detected section 3 exception handling rev. 6.00 aug 04, 2006 page 88 of 626 rej09b0144-0600 bit 3: irq 3 edge select (ieg3) bit 3 selects the input sensing of the irq 3 pin and tmif pin. bit 3 ieg3 description 0 falling edge of irq 3 and tmif pin input is detected (initial value) 1 rising edge of irq 3 and tmif pin input is detected bit 2: irq 2 edge select (ieg2) bit 2 selects the input sensing of pin irq 2 . bit 2 ieg2 description 0 falling edge of irq 2 pin input is detected (initial value) 1 rising edge of irq 2 pin input is detected bit 1: irq 1 edge select (ieg1) bit 3 selects the input sensing of the irq 1 pin and tmic pin. bit 1 ieg1 description 0 falling edge of irq 1 and tmic pin input is detected (initial value) 1 rising edge of irq 1 and tmic pin input is detected bit 0: irq 0 edge select (ieg0) bit 0 selects the input sensing of pin irq 0 . bit 0 ieg0 description 0 falling edge of irq 0 pin input is detected (initial value) 1 rising edge of irq 0 pin input is detected section 3 exception handling rev. 6.00 aug 04, 2006 page 89 of 626 rej09b0144-0600 2. interrupt enable register 1 (ienr1) bit initial value read/write 7 ienta 0 r/w 6 ? 0 r/w 5 ienwp 0 r/w 4 ien4 0 r/w 3 ien3 0 r/w 0 ien0 0 r/w 2 ien2 0 r/w 1 ien1 0 r/w ienr1 is an 8-bit read/write register that enables or disables interrupt requests. bit 7: timer a interrupt enable (ienta) bit 7 enables or disables timer a overflow interrupt requests. bit 7 ienta description 0 disables timer a interrupt requests (initial value) 1 enables timer a interrupt requests bit 6: reserved bit bit 6 is a readable/writable reserved bit. it is initialized to 0 by a reset. bit 5: wakeup interrupt enable (ienwp) bit 5 enables or disables wkp 7 to wkp 0 interrupt requests. bit 5 ienwp description 0 disables wkp 7 to wkp 0 interrupt requests (initial value) 1 enables wkp 7 to wkp 0 interrupt requests bits 4 to 0: irq 4 to irq 0 interrupt enable (ien4 to ien0) bits 4 to 0 enable or disable irq 4 to irq 0 interrupt requests. bit n ienn description 0 disables interrupt requests from pin irq n (initial value) 1 enables interrupt requests from pin irq n (n = 4 to 0) section 3 exception handling rev. 6.00 aug 04, 2006 page 90 of 626 rej09b0144-0600 3. interrupt enable register 2 (ienr2) bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 ? 0 r/w 4 ientg 0 r/w 3 ientfh 0 r/w 0 ienec 0 r/w 2 ientfl 0 r/w 1 ientc 0 r/w ienr2 is an 8-bit read/write register that enables or disables interrupt requests. bit 7: direct transfer interrupt enable (iendt) bit 7 enables or disables direct transfer interrupt requests. bit 7 iendt description 0 disables direct transfer interrupt requests (initial value) 1 enables direct transfer interrupt requests bit 6: a/d converter interrupt enable (ienad) bit 6 enables or disables a/d converter interrupt requests. bit 6 ienad description 0 disables a/d converter interrupt requests (initial value) 1 enables a/d converter interrupt requests bit 5: reserved bit bit 5 is a readable/writable reserved bit. it is initialized to 0 by a reset. bit 4: timer g interrupt enable (ientg) bit 4 enables or disables timer g input capture or overflow interrupt requests. bit 4 ientg description 0 disables timer g interrupt requests (initial value) 1 enables timer g interrupt requests section 3 exception handling rev. 6.00 aug 04, 2006 page 91 of 626 rej09b0144-0600 bit 3: timer fh interrupt enable (ientfh) bit 3 enables or disables timer fh compare match and overflow interrupt requests. bit 3 ientfh description 0 disables timer fh interrupt requests (initial value) 1 enables timer fh interrupt requests bit 2: timer fl interrupt enable (ientfl) bit 2 enables or disables timer fl compare match and overflow interrupt requests. bit 2 ientfl description 0 disables timer fl interrupt requests (initial value) 1 enables timer fl interrupt requests bit 1: timer c interrupt enable (ientc) bit 1 enables or disables timer c overflow and underflow interrupt requests. bit 1 ientc description 0 disables timer c interrupt requests (initial value) 1 enables timer c interrupt requests bit 0: asynchronous event counter interrupt enable (ienec) bit 0 enables or disables asynchronous event counter interrupt requests. bit 0 ienec description 0 disables asynchronous event counter interrupt requests (initial value) 1 enables asynchronous event counter interrupt requests for details of sci3-1 and sci3-2 interrupt control, see section 10.2.6, serial control register 3 (scr3). section 3 exception handling rev. 6.00 aug 04, 2006 page 92 of 626 rej09b0144-0600 4. interrupt request register 1 (irr1) bit initial value read/write 7 irrta 0 r/w 6 ? 0 r/w 5 ? 1 ? 4 irri4 0 r/w 3 irri3 0 r/w 0 irri0 0 r/w 2 irri2 0 r/w 1 irri1 0 r/w ** * **** note: * only a write of 0 for flag clearing is possible irr1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer a or irq 4 to irq 0 interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7: timer a interrupt request flag (irrta) bit 7 irrta description 0 clearing condition: (initial value) when irrta = 1, it is cleared by writing 0 1 setting condition: when the timer a counter value overflows from h'ff to h'00 bit 6: reserved bit bit 6 is a readable/writable reserved bit. it is initialized to 0 by a reset. bit 5: reserved bit bit 5 is reserved; it is always read as 1 and cannot be modified. section 3 exception handling rev. 6.00 aug 04, 2006 page 93 of 626 rej09b0144-0600 bits 4 to 0: irq 4 to irq 0 interrupt request flags (irri4 to irri0) bit n irrin description 0 clearing condition: (initial value) when irrin = 1, it is cleared by writing 0 1 setting condition: when pin irq n is designated for interrupt input and the designated signal edge is input (n = 4 to 0) 5. interrupt request register 2 (irr2) bit initial value read/write 7 irrdt 0 r/w 6 irrad 0 r/w 5 ? 0 r/w 4 irrtg 0 r/w 3 irrtfh 0 r/w 0 irrec 0 r/w 2 irrtfl 0 r/w 1 irrtc 0 r/w ** ***** note: * only a write of 0 for flag clearing is possible irr2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, a/d converter, timer g, timer fh, timer fc, or timer c interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7: direct transfer interrupt request flag (irrdt) bit 7 irrdt description 0 clearing condition: (initial value) when irrdt = 1, it is cleared by writing 0 1 setting condition: when a direct transfer is made by executing a sleep instruction while dton = 1 in syscr2 section 3 exception handling rev. 6.00 aug 04, 2006 page 94 of 626 rej09b0144-0600 bit 6: a/d converter interrupt request flag (irrad) bit 6 irrad description 0 clearing condition: (initial value) when irrad = 1, it is cleared by writing 0 1 setting condition: when a/d conversion is completed and adsf is cleared to 0 in adsr bit 5: reserved bit bit 5 is a readable/writable reserved bit. it is initialized to 0 by a reset. bit 4: timer g interrupt request flag (irrtg) bit 4 irrtg description 0 clearing condition: (initial value) when irrtg = 1, it is cleared by writing 0 1 setting condition: when the tmig pin is designated for tmig input and the designated signal edge is input, or when tcg overflows while ovie is set to 1 in tmg bit 3: timer fh interrupt request flag (irrtfh) bit 3 irrtfh description 0 clearing condition: (initial value) when irrtfh = 1, it is cleared by writing 0 1 setting condition: when tcfh and ocrfh match in 8-bit timer mode, or when tcf (tcfl, tcfh) and ocrf (ocrfl, ocrfh) match in 16-bit timer mode section 3 exception handling rev. 6.00 aug 04, 2006 page 95 of 626 rej09b0144-0600 bit 2: timer fl interrupt request flag (irrtfl) bit 2 irrtfl description 0 clearing condition: (initial value) when irrtfl= 1, it is cleared by writing 0 1 setting condition: when tcfl and ocrfl match in 8-bit timer mode bit 1: timer c interrupt request flag (irrtc) bit 1 irrtc description 0 clearing condition: (initial value) when irrtc= 1, it is cleared by writing 0 1 setting condition: when the timer c counter value overflows (from h'ff to h'00) or underflows (from h'00 to h'ff) bit 0: asynchronous event counter interrupt request flag (irrec) bit 0 irrec description 0 clearing condition: (initial value) when irrec = 1, it is cleared by writing 0 1 setting condition: when ech overflows in 16-bit counter mode, or ech or ecl overflows in 8-bit counter mode section 3 exception handling rev. 6.00 aug 04, 2006 page 96 of 626 rej09b0144-0600 6. wakeup interrupt request register (iwpr) bit initial value read/write 7 iwpf7 0 r/w 6 iwpf6 0 r/w 5 iwpf5 0 r/w 4 iwpf4 0 r/w 3 iwpf3 0 r/w 0 iwpf0 0 r/w 2 iwpf2 0 r/w 1 iwpf1 0 r/w ** **** ** note: * only a write of 0 for flag clearing is possible iwpr is an 8-bit read/write register containing wakeup interrupt request flags. when one of pins wkp 7 to wkp 0 is designated for wakeup input and a rising or falling edge is input at that pin, the corresponding flag in iwpr is set to 1. a flag is not cleared automatically when the corresponding interrupt is accepted. flags must be cleared by writing 0. bits 7 to 0: wakeup interrupt request flags (iwpf7 to iwpf0) bit n iwpfn description 0 clearing condition: (initial value) when iwpfn= 1, it is cleared by writing 0 1 setting condition: when pin wkp n is designated for wakeup input and a rising or falling edge is input at that pin (n = 7 to 0) section 3 exception handling rev. 6.00 aug 04, 2006 page 97 of 626 rej09b0144-0600 7. wakeup edge select register (wegr) bit initial value read/write 7 wkegs7 0 r/w 6 wkegs6 0 r/w 5 wkegs5 0 r/w 4 wkegs4 0 r/w 3 wkegs3 0 r/w 0 wkegs0 0 r/w 2 wkegs2 0 r/w 1 wkegs1 0 r/w wegr is an 8-bit read/write register that specifies rising or falling edge sensing for pins wkp n. wegr is initialized to h'00 by a reset. bit n: wkp n edge select (wkegsn) bit n selects wkp n pin input sensing. bit n wkegsn description 0 wkp n pin falling edge detected (initial value) 1 wkp n pin rising edge detected (n = 7 to 0) 3.3.3 external interrupts there are 13 external interrupts: irq 4 to irq 0 and wkp 7 to wkp 0 . 1. interrupts wkp 7 to wkp 0 interrupts wkp 7 to wkp 0 are requested by either rising or falling edge input to pins wkp 7 to wkp 0 . when these pins are designated as pins wkp 7 to wkp 0 in port mode register 5 and a rising or falling edge is input, the corresponding bit in iwpr is set to 1, requesting an interrupt. recognition of wakeup interrupt requests can be disabled by clearing the ienwp bit to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when wkp 7 to wkp 0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector number 9 is assigned to interrupts wkp 7 to wkp 0 . all eight interrupt sources have the same vector number, so the interrupt-handling routine must discriminate the interrupt source. section 3 exception handling rev. 6.00 aug 04, 2006 page 98 of 626 rej09b0144-0600 2. interrupts irq 4 to irq 0 interrupts irq 4 to irq 0 are requested by input signals to pins irq 4 to irq 0 . these interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg4 to ieg0 in iegr. when these pins are designated as pins irq 4 to irq 0 in port mode register 3 and 1 and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. recognition of these interrupt requests can be disabled individually by clearing bits ien4 to ien0 to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when irq 4 to irq 0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector numbers 8 to 4 are assigned to interrupts irq 4 to irq 0 . the order of priority is from irq 0 (high) to irq 4 (low). table 3.2 gives details. 3.3.4 internal interrupts there are 23 internal interrupts that can be requested by the on-chip peripheral modules. when a peripheral module requests an interrupt, the corresponding bit in irr1 or irr2 is set to 1. recognition of individual interrupt requests can be disabled by clearing the corresponding bit in ienr1 or ienr2. all these interrupts can be masked by setting the i bit to 1 in ccr. when internal interrupt handling is initiated, the i bit is set to 1 in ccr. vector numbers from 20 to 11 are assigned to these interrupts. table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. section 3 exception handling rev. 6.00 aug 04, 2006 page 99 of 626 rej09b0144-0600 3.3.5 interrupt operations interrupts are controlled by an interrupt controller. figure 3.2 shows a block diagram of the interrupt controller. figure 3.3 shows the flow up to interrupt acceptance. interrupt controller priority decision logic interrupt request ccr (cpu) i external or internal interrupts external interrupts or internal interrupt enable signals figure 3.2 block diagram of interrupt controller interrupt operation is described as follows. ? when an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. ? when the interrupt controller receives an interrupt request, it sets the interrupt request flag. ? from among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (refer to table 3.2 for a list of interrupt priorities.) ? the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending. section 3 exception handling rev. 6.00 aug 04, 2006 page 100 of 626 rej09b0144-0600 ? if the interrupt is accepted, after processing of the current instruction is completed, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.4. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. ? the i bit of ccr is set to 1, masking further interrupts. ? the vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. notes: 1. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (i = 1). 2. if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. section 3 exception handling rev. 6.00 aug 04, 2006 page 101 of 626 rej09b0144-0600 pc contents saved ccr contents saved i 1 i = 0 program execution state no yes yes no legend: pc: ccr: i: program counter condition code register i bit of ccr ien0 = 1 no yes iendt = 1 no yes irrdt = 1 no yes branch to interrupt handling routine irri0 = 1 no yes ien1 = 1 no yes irri1 = 1 no yes ien2 = 1 no yes irri2 = 1 figure 3.3 flow up to interrupt acceptance section 3 exception handling rev. 6.00 aug 04, 2006 page 102 of 626 rej09b0144-0600 pc and ccr saved to stack sp (r7) sp ? 1 sp ? 2 sp ? 3 sp ? 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling legend: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr pc h pc l 1. 2. * pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word access, starting from an even-numbered address. ignored on return. * figure 3.4 stack state after completion of interrupt exception handling figure 3.5 shows a typical interrupt sequence. section 3 exception handling rev. 6.00 aug 04, 2006 page 103 of 626 rej09b0144-0600 vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ? 2 (6) sp ? 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.5 interrupt sequence section 3 exception handling rev. 6.00 aug 04, 2006 page 104 of 626 rej09b0144-0600 3.3.6 interrupt response time table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. table 3.4 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 13 15 to 27 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction. section 3 exception handling rev. 6.00 aug 04, 2006 page 105 of 626 rej09b0144-0600 3.4 application notes 3.4.1 notes on stack area use when word data is accessed in the h8/3864 group, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @?sp) or pop rn (mov.w @sp+, rn) to save or restore register values. setting an odd address in sp may cause a program to crash. an example is shown in figure 3.6. pc pc r1l pc sp sp sp h'fefc h'fefd h'feff h l l mov. b r1l, @ ? r7 sp set to h'feff stack accessed beyond sp bsr instruction contents of pc are lost h legend: pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer figure 3.6 operation when odd address is set in sp when ccr contents are saved to the stack during interrupt exception handling or restored when rte is executed, this also takes place in word size. both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to ccr while the odd address contents are ignored. section 3 exception handling rev. 6.00 aug 04, 2006 page 106 of 626 rej09b0144-0600 3.4.2 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. when an external interrupt pin function is switched by rewriting the port mode register that controls pins irq 4 to irq 0 , wkp 7 to wkp 0 , the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. be sure to clear the interrupt request flag to 0 after switching pin functions. table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. table 3.5 conditions under which interrupt request flag is set to 1 interrupt request flags set to 1 conditions irr1 irri4 when pmr1 bit irq4 is changed from 0 to 1 while pin irq 4 is low and iegr bit ieg4 = 0. when pmr1 bit irq4 is changed from 1 to 0 while pin irq 4 is low and iegr bit ieg4 = 1. irri3 when pmr1 bit irq3 is changed from 0 to 1 while pin irq 3 is low and iegr bit ieg3 = 0. when pmr1 bit irq3 is changed from 1 to 0 while pin irq 3 is low and iegr bit ieg3 = 1. irri2 when pmr1 bit irq2 is changed from 0 to 1 while pin irq 2 is low and iegr bit ieg2 = 0. when pmr1 bit irq2 is changed from 1 to 0 while pin irq 2 is low and iegr bit ieg2 = 1. irri1 when pmr1 bit irq1 is changed from 0 to 1 while pin irq 1 is low and iegr bit ieg1 = 0. when pmr1 bit irq1 is changed from 1 to 0 while pin irq 1 is low and iegr bit ieg1 = 1. irri0 when pmr3 bit irq0 is changed from 0 to 1 while pin irq 0 is low and iegr bit ieg0 = 0. when pmr3 bit irq0 is changed from 1 to 0 while pin irq 0 is low and iegr bit ieg0 = 1. iwpr iwpf7 when pmr5 bit wkp7 is changed from 0 to 1 while pin wkp 7 is low. iwpf6 when pmr5 bit wkp6 is changed from 0 to 1 while pin wkp 6 is low. iwpf5 when pmr5 bit wkp5 is changed from 0 to 1 while pin wkp 5 is low. iwpf4 when pmr5 bit wkp4 is changed from 0 to 1 while pin wkp 4 is low. iwpf3 when pmr5 bit wkp3 is changed from 0 to 1 while pin wkp 3 is low. iwpf2 when pmr5 bit wkp2 is changed from 0 to 1 while pin wkp 2 is low. iwpf1 when pmr5 bit wkp1 is changed from 0 to 1 while pin wkp 1 is low. iwpf0 when pmr5 bit wkp0 is changed from 0 to 1 while pin wkp 0 is low. section 3 exception handling rev. 6.00 aug 04, 2006 page 107 of 626 rej09b0144-0600 figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. if the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. an alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 ccr i bit 0 figure 3.7 port mode register setting and interrupt request flag clearing procedure section 3 exception handling rev. 6.00 aug 04, 2006 page 108 of 626 rej09b0144-0600 3.4.3 method for clearing interrupt request flags use the recommended method, given below when clearing the flags of interrupt request registers (irr1, irr2, iwpr). ? recommended method use a single instruction to clear flags. the bit control instruction and byte-size data transfer instruction can be used. two examples of program code for clearing irri1 (bit 1 of irr1) are given below. bclr #1, @irr1:8 mov.b r1l, @irr1:8 (set the value of r1l to b'11111101) ? example of a malfunction when flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. here is an example in which irri0 is cleared and disabled in the process of clearing irri1 (bit 1 of irr1). mov.b @irr1:8,r1l ......... irri0 = 0 at this time and.b #b'11111101,r1l ..... here, irri0 = 1 mov.b r1l,@irr1:8 ......... irri0 is cleared to 0 in the above example, it is assumed that an irq0 interrupt is generated while the and.b instruction is executing. the irq0 interrupt is disabled because, although the original objective is clearing irri1, irri0 is also cleared. section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 109 of 626 rej09b0144-0600 section 4 clock pulse generators 4.1 overview clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 block diagram figure 4.1 shows a block diagram of the clock pulse generators. system clock oscillator system clock divider (1/2) subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider system clock pulse generator subclock pulse generator prescaler s (13 bits) prescaler w (5 bits) osc osc 1 2 x x excl * note: * h8/38327 group and h8/38427 group only 1 2 osc (f ) osc w w (f ) w /2 osc /2 w /8 w sub /2 to /8192 /2 w /4 w /8 to /128 w w osc /128 osc /64 osc /32 osc /16 /4 w figure 4.1 block diagram of clock pulse generators 4.1.2 system clock and subclock the basic clock signals that drive the cpu and on-chip peripheral modules are and sub . four of the clock signals have names: is the system clock, sub is the subclock, osc is the oscillator clock, and w is the watch clock. the clock signals available for use by peripheral modules are /2, /4, /8, /16, /32, /64, /128, /256, /512, /1024, /2048, /4096, /8192, w , w /2, w /4, w /8, w /16, w /32, w /64, and w /128. the clock requirements differ from one module to another. section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 110 of 626 rej09b0144-0600 4.2 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. connecting a crystal oscillator figure 4.2 shows a typical method of connecting a crystal oscillator. for information on recommended resonators, see the product ac characteristics listed in section 15, electrical characteristics. please consult with the resonator manufacturer when selecting a resonator model. 1 2 c 1 c 2 osc osc r = 1 m 20% f ? r f figure 4.2 typical connection to crystal oscillator 2. connecting a ceramic oscillator figure 4.3 shows a typical method of connecting a ceramic oscillator. for information on recommended resonators, see the product ac characteristics listed in section 15, electrical characteristics. please consult with the resonator manufacturer when selecting a resonator model. 1 2 c 1 c 2 osc osc r f r = 1 m 20% f ? figure 4.3 typical connection to ceramic oscillator 3. notes on board design when generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (see figure 4.4.) section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 111 of 626 rej09b0144-0600 the board should be designed so that the oscillator and load capacitors are located as close as possible to pins osc 1 and osc 2 . osc osc c 1 c 2 signal a signal b 2 1 to be avoided figure 4.4 board design of oscillator circuit 4. external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 4.5 shows a typical connection. 1 2 osc osc external clock input open figure 4.5 external clock input (example) frequency oscillator clock ( osc ) duty cycle 45% to 55% note: the circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer. the circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board. when using the oscillator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 112 of 626 rej09b0144-0600 4.3 subclock generator 1. connecting a 32.768 khz/38.4 khz crystal oscillator clock pulses can be supplied to the subclock divider by connecting a 32.768 khz/38.4 khz crystal oscillator, as shown in figure 4.6. follow the same precautions as noted under 3. notes on board design for the system clock in 4.2. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 note: circuit constants should be determined in consultation with the resonator manufacturer. 32.768 khz nihon denpa kogyo mx73p 38.4 khz vtc-200 seiko instrument inc. oscillation frequency manufacturer products name figure 4.6 typical connection to 32.768 khz/38.4 khz crystal oscillator (subclock) figure 4.7 shows the equivalent circuit of the 32.768 khz/38.4 khz crystal oscillator. c s c 0 lr s x 1 x 2 c = 1.5 pf typ r = 14 k typ f = 32.768 khz/38.4khz 0 s w ? s figure 4.7 equivalent circuit of 32.768 khz/38.4 khz crystal oscillator section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 113 of 626 rej09b0144-0600 2. pin connection when not using subclock when the subclock is not used, connect pin x 1 to gnd and leave pin x 2 open, as shown in figure 4.8. x x 1 2 gnd open figure 4.8 pin connection when not using subclock 3. external clock input ? h8/3827r group and h8/3827s group connect the external clock to the x 1 pin and leave the x 2 pin open, as shown in figure 4.9 (a). open x 1 external clock input x 2 figure 4.9 (a) pin connection when inputting external clock frequency subclock ( w) duty 45% to 55% section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 114 of 626 rej09b0144-0600 ? h8/38327 group and h8/38427 group connect pin x 1 to gnd and leave pin x 2 open. input an external clock to pin excl. set bit excl in register pmr2 to 1 to supply the external clock to the internal components of the device. a connection example is shown in figure 4.9 (b). x 1 p3 1 /ud/excl external clock input x 2 open gnd figure 4.9 (b) pin connection when inputting external clock (h8/38327 group and h8/38427 group) frequency subclock ( w) duty 45% to 55% section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 115 of 626 rej09b0144-0600 4.4 prescalers the h8/3864 group is equipped with two on-chip prescalers having different input clocks (prescaler s and prescaler w). prescaler s is a 13-bit counter using the system clock ( ) as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. prescaler w is a 5-bit counter using a 32.768 khz or 38.4 khz signal divided by 4 ( w /4) as its input clock. its prescaled outputs are used by timer a as a time base for timekeeping. 1. prescaler s (pss) prescaler s is a 13-bit counter using the system clock ( ) as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by timer a, timer c, timer f, timer g, sci3-1, sc3-2, the a/d converter, the lcd controller, the watchdog timer, and the 14-bit pwm. the divider ratio can be set separately for each on-chip peripheral function. in active (medium-speed) mode the clock input to prescaler s is osc/16, osc/32, osc/64, or osc/128. 2. prescaler w (psw) prescaler w is a 5-bit counter using a 32.768 khz/38.4 khz signal divided by 4 ( w /4) as its input clock. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x1 and x2. prescaler w can be reset by setting 1s in bits tma3 and tma2 of timer mode register a (tma). output from prescaler w can be used to drive timer a, in which case timer a functions as a time base for timekeeping. section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 116 of 626 rej09b0144-0600 4.5 note on oscillators oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask rom, ztat?, and f-ztat? versions, referring to the examples shown in this section. oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the oscillator element manufacturer. design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. (vss) test osc 1 osc 2 vss x 2 x 1 p1 7 figure 4.10 example of crystal and ceramic oscillator element arrangement figure 4.11 (1) shows an example measuring circuit with the negative resistance suggested by the oscillator manufacturer. note that if the negative resistance of the circuit is less than that suggested by the oscillator manufacturer, it may be difficult to start the main oscillator. if it is determined that oscillation is not occurring because the negative resistance is lower than the level suggested by the oscillator manufacturer, the circuit may be modified as shown in figure 4.11 (2) through (4). which of the modification suggestions to use and the capacitor capacitance should be decided based upon an evaluation of factors such as the negative resistance and the frequency deviation. section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 117 of 626 rej09b0144-0600 (1) negative resistance measuring circuit (2) oscillator circuit modification suggestion 1 (3) oscillator circuit modification suggestion 2 (4) oscillator circuit modification suggestion 3 c3 osc1 osc2 rf c1 c2 negative resistance, addition of ? r osc1 osc2 rf c1 c2 modification point modification point modification point osc1 osc2 rf c1 c2 osc1 osc2 rf c1 c2 figure 4.11 negative resistance measurement and circuit modification suggestions 4.5.1 definition of oscillation stabilization wait time figure 4.12 shows the oscillation waveform (osc 2 ), system clock ( ), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator. as shown in figure 4.12, as the system clock oscillator is halted in standby mode, watch mode, and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the sum of the following two times (oscillation stabilization time and wait time) is required. section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 118 of 626 rej09b0144-0600 1. oscillation stabilization time (t rc ) the time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. wait time the time required for the cpu and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized. the wait time setting is selected with standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in system control register 1 (syscr1)). oscillation waveform (osc 2 ) system clock ( ) oscillation stabilization time operating mode standby mode, watch mode, or subactive mode wait time oscillation stabilization wait time active (high-speed) mode or active (medium-speed) mode interrupt accepted figure 4.12 oscillation stabilization wait time when standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to change at the point at which the interrupt is accepted. therefore, when an oscillator element is connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is halted, the time from the point at which this oscillation waveform starts to change until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes?that is, the oscillation stabilization time?is required. section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 119 of 626 rej09b0144-0600 the oscillation stabilization time in the case of these state transitions is the same as the oscillation stabilization time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time t rc " in the ac characteristics. meanwhile, once the system clock has halted, a wait time of at least 8 states is necessary in order for the cpu and peripheral functions to operate normally. thus, the time required from interrupt generation until operation of the cpu and peripheral functions is the sum of the above described oscillation stabilization time and wait time. this total time is called the oscillation stabilization wait time, and is expressed by equation (1) below. oscillation stabilization wait time = oscillation stabilization time + wait time = t rc + (8 to 131,072 states) ................. (1) therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation stabilization wait time. in particular, since the oscillation stabilization time is affected by installation circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the oscillator element manufacturer. 4.5.2 notes on use of crystal oscillator element (excluding ceramic oscillator element) when a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. depending on the individual crystal oscillator element characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. in this state, the oscillation waveform may be disrupted, leading to an unstable system clock and erroneous operation of the microcomputer. if erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in system control register 1 (syscr1)) to give a longer wait time. for example, if erroneous operation occurs with a wait time setting of 16 states, check the operation with a wait time setting of 8,192 states or more. if the same kind of erroneous operation occurs after a reset as after a state transition, hold the res pin low for a longer period. section 4 clock pulse generators rev. 6.00 aug 04, 2006 page 120 of 626 rej09b0144-0600 section 5 power-down modes rev. 6.00 aug 04, 2006 page 121 of 626 rej09b0144-0600 section 5 power-down modes 5.1 overview the h8/3827r group has nine modes of operation after a reset. these include eight power-down modes, in which power dissipation is significantly reduced. table 5.1 gives a summary of the nine operating modes. table 5.1 operating modes operating mode description active (high-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock in high-speed operation active (medium-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock in low-speed operation subactive mode the cpu is operable on the subclock in low-speed operation sleep (high-speed) mode the cpu halts. on-chip peripheral functions are operable on the system clock sleep (medium-speed) mode the cpu halts. on-chip peripheral functions operate at a frequency of 1/64, 1/32, 1/16, or 1/8 of the system clock frequency subsleep mode the cpu halts. the time-base function of timer a, timer c, timer g, timer f,wdt, sci3-1, sci3-2, aec, and lcd controller/driver are operable on the subclock watch mode the cpu halts. the time-base function of timer a, timer f, timer g, aec, and lcd controller/driver are operable on the subclock standby mode the cpu and all on-chip peripheral functions halt module standby mode individual on-chip peripheral functions specified by software enter standby mode and halt of these nine operating modes, all but the active (high-speed) mode are power-down modes. in this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode. figure 5.1 shows the transitions among these operation modes. table 5.2 indicates the internal states in each mode. section 5 power-down modes rev. 6.00 aug 04, 2006 page 122 of 626 rej09b0144-0600 program halt state sleep instruction (e) sleep instruction (c) sleep instruction (h) sleep instruction (i) sleep instruction (g) sleep instruction (f) program execution state sleep instruction (a) program halt state sleep instruction (i) power-down modes a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that interrupt handling is performed after the interrupt is accepted. details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 to 5.9. notes: 1. 2. mode transition conditions (1) (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) lson mson ssby dton 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 * : don?t care mode transition conditions (2) (1) interrupt sources timer a, timer f, timer g interrupt, irq 0 interrupt, wkp 7 to wkp 0 interrupts timer a, timer c, timer f, timer g, sci3-1, sci3-2 interrupt, irq 4 to irq 0 interrupts, wkp 7 to wkp 0 interrupts, aec all interrupts irq 1 or irq 0 interrupt, wkp 7 to wkp 0 interrupts (2) (3) (4) (3) (3) (2) (1) (4) (4) (1) standby mode watch mode subactive mode active (medium-speed) mode active (high-speed) mode sleep (high-speed) mode sleep (medium-speed) mode subsleep mode sleep instruct ion ( a ) slee p instructio n (e) sleep instruction (d) sleep instruction (b) sleep instruction ( j ) (1) slee p instructio n ( e ) slee p instruction (b) tma3 1 0 1 1 1 1 sleep instruction (d) reset state * * * * * * * * * figure 5.1 mode transition diagram section 5 power-down modes rev. 6.00 aug 04, 2006 page 123 of 626 rej09b0144-0600 table 5.2 internal state in each operating mode active mode sleep mode function high- speed medium- speed high- speed medium- speed watch mode subactive mode subsleep mode standby mode system clock oscillator functions functions functions functions halted halted halted halted subclock oscillator functions functions functions functions functions functions functions functions instructions functions functions halted halted halted functions halted halted cpu operations ram retained retained retained retained retained registers i/o ports retained * 1 irq 0 functions functions functions functions functions functions functions functions external interrupts irq 1 retained * 6 irq 2 retained * 6 irq 3 irq 4 wkp 0 functions functions functions functions functions functions functions functions wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 timer a functions functions functions functions functions * 5 functions * 5 functions * 5 retained peripheral functions asynchronous counter functions * 8 functions functions functions * 8 timer c retained functions/ retained * 2 functions/ retained * 2 retained wdt functions/ retained * 7 retained timer g, timer f functions/ retained * 9 functions/ retained * 2 functions/ retained * 2 sci3-1 reset sci3-2 reset functions/ retained * 3 functions/ retained * 3 pwm retained retained retained retained a/d converter retained retained retained retained lcd functions/ retained * 4 functions/ retained * 4 functions/ retained * 4 retained notes: 1. register contents are retained, but output is high-impedance state. 2. functions if an external clock or the w /4 internal clock is selected; otherwise halted and retained. 3. functions if w /2 is selected as the internal clock; otherwise halted and retained. 4. functions if w , w /2 or w /4 is selected as the operating clock; otherwise halted and retained. 5. functions if the timekeeping time-base function is selected. 6. external interrupt requests are ignored. interrupt request register contents are not altered. 7. functions if w /32 is selected as the internal clock; otherwise halted and retained. 8. incrementing is possible, but interrupt generation is not. 9. functions if the w /4 internal clock is selected; otherwise halted and retained. section 5 power-down modes rev. 6.00 aug 04, 2006 page 124 of 626 rej09b0144-0600 5.1.1 system control registers the operation mode is selected using the system control registers described in table 5.3. table 5.3 system control registers name abbr. r/w initial value address system control register 1 syscr1 r/w h'07 h'fff0 system control register 2 syscr2 r/w h'f0 h'fff1 1. system control register 1 (syscr1) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 lson 0 r/w 0 ma0 1 r/w 2 ? 1 ? 1 ma1 1 r/w syscr1 is an 8-bit read/write register for control of the power-down modes. upon reset, syscr1 is initialized to h'07. bit 7: software standby (ssby) this bit designates transition to standby mode or watch mode. bit 7 ssby description 0 ? when a sleep instruction is executed in active mode, (initial value) a transition is made to sleep mode ? when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode 1 ? when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode section 5 power-down modes rev. 6.00 aug 04, 2006 page 125 of 626 rej09b0144-0600 bits 6 to 4: standby timer select 2 to 0 (sts2 to sts0) these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. the designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 000wait time = 8, 192 states (initial value) 001wait time = 16,384 states 010wait time = 32,768 states 011wait time = 65,536 states 100wait time = 131,072 states 101wait time = 2 states(external clock mode) 110wait time = 8 states 111wait time = 16 states note: in the case that external clock is input, set up the ?standby timer select? selection to external clock mode before mode transition. also, do not set up to external clock mode, in the case that it does not use external clock. bit 3: low speed on flag (lson) this bit chooses the system clock ( ) or subclock ( sub ) as the cpu operating clock when watch mode is cleared. the resulting operation mode depends on the combination of other control bits and interrupt input. bit 3 lson description 0 the cpu operates on the system clock ( ) (initial value) 1 the cpu operates on the subclock ( sub ) bits 2: reserved bits bit 2 is reserved: it is always read as 1 and cannot be modified. section 5 power-down modes rev. 6.00 aug 04, 2006 page 126 of 626 rej09b0144-0600 bits 1 and 0: active (medium-speed) mode clock select (ma1, ma0) bits 1 and 0 choose osc /128, osc /64, osc /32, or osc /16 as the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. ma1 and ma0 should be written in active (high-speed) mode or subactive mode. bit 1 ma1 bit 0 ma0 description 00 osc /16 01 osc /32 10 osc /64 11 osc /128 (initial value) 2. system control register 2 (syscr2) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 nesel 1 r/w 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w syscr2 is an 8-bit read/write register for power-down mode control. bits 7 to 5: reserved bits these bits are reserved; they are always read as 1, and cannot be modified. bit 4: noise elimination sampling frequency select (nesel) this bit selects the frequency at which the watch clock signal ( w ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock ( osc ) generated by the system clock pulse generator. when osc = 2 to 16 mhz, clear nesel to 0. bit 4 nesel description 0 sampling rate is osc /16 1 sampling rate is osc /4 (initial value) section 5 power-down modes rev. 6.00 aug 04, 2006 page 127 of 626 rej09b0144-0600 bit 3: direct transfer on flag (dton) this bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a sleep instruction is executed. the mode to which the transition is made after the sleep instruction is executed depends on a combination of this and other control bits. bit 3 dton description 0 ? when a sleep instruction is executed in active mode, (initial value) a transition is made to standby mode, watch mode, or sleep mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode 1 ? when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 ? when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 ? when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1 bit 2: medium speed on flag (mson) after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. bit 2 mson description 0 operation in active (high-speed) mode (initial value) 1 operation in active (medium-speed) mode section 5 power-down modes rev. 6.00 aug 04, 2006 page 128 of 626 rej09b0144-0600 bits 1 and 0: subactive mode clock select (sa1 and sa0) these bits select the cpu clock rate ( w /2, w /4, or w /8) in subactive mode. sa1 and sa0 cannot be modified in subactive mode. bit 1 sa1 bit 0 sa0 description 00 w /8 (initial value) 01 w /4 1 * w /2 * : don?t care 5.2 sleep mode 5.2.1 transition to sleep mode 1. transition to sleep (high-speed) mode the system goes from active mode to sleep (high-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson and dton bits in syscr2 are cleared to 0. in sleep mode cpu operation is halted but the on-chip peripheral functions. cpu register contents are retained. 2. transition to sleep (medium-speed) mode the system goes from active mode to sleep (medium-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is cleared to 0. in sleep (medium-speed) mode, as in sleep (high-speed) mode, cpu operation is halted but the on-chip peripheral functions are operational. the clock frequency in sleep (medium-speed) mode is determined by the ma1 and ma0 bits in syscr1. cpu register contents are retained. furthermore, it sometimes acts with half state early timing at the time of transition to sleep (medium-speed) mode. section 5 power-down modes rev. 6.00 aug 04, 2006 page 129 of 626 rej09b0144-0600 5.2.2 clearing sleep mode sleep mode is cleared by any interrupt (timer a, timer c, timer f, timer g, asynchronous counter, irq 4 to irq 0 , wkp 7 to wkp 0 , sci3-1, sci3-2, a/d converter, or), or by input at the res pin. ? clearing by interrupt when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. a transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. interrupt signal and system clock are mutually asynchronous. synchronization error time in a maximum is 2/ (s). ? clearing by res input when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 5.2.3 clock frequency in sleep (medium-speed) mode operation in sleep (medium-speed) mode is clocked at the frequency designated by the ma1 and ma0 bits in syscr1. 5.3 standby mode 5.3.1 transition to standby mode the system goes from active mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and bit tma3 in tma is cleared to 0. in standby mode the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of cpu registers, on-chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be further retained down to a minimum ram data retention voltage. the i/o ports go to the high-impedance state. section 5 power-down modes rev. 6.00 aug 04, 2006 page 130 of 626 rej09b0144-0600 5.3.2 clearing standby mode standby mode is cleared by an interrupt (irq 1 or irq 0 ), wkp 7 to wkp 0 or by input at the res pin. ? clearing by interrupt when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. operation resumes in active (high-speed) mode if mson = 0 in syscr2, or active (medium-speed) mode if mson = 1. standby mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. ? clearing by res input when the res pin goes low, the system clock pulse generator starts. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes. section 5 power-down modes rev. 6.00 aug 04, 2006 page 131 of 626 rej09b0144-0600 5.3.3 oscillator settling time after standby mode is cleared bits sts2 to sts0 in syscr1 should be set as follows. ? when a crystal oscillator is used the table below gives settings for various operating frequencies. set bits sts2 to sts0 for a waiting time at least as long as the oscillation settling time. table 5.4 clock frequency and settling time (times are in ms) sts2 sts1 sts0 waiting time 2 mhz 1 mhz 0008, 192 states 4.1 8.2 0 0 1 16,384 states 8.2 16.4 0 1 0 32,768 states 16.4 32.8 0 1 1 65,536 states 32.8 65.5 1 0 0 131,072 states 65.5 131.1 1012 states (use prohibited)0.0010.002 1108 states 0.0040.008 1 1 1 16 states 0.008 0.016 ? when an external clock is used sts2 = 1, sts1 = 0, and sts0 = 1 should be set. other values possible use, but cpu sometimes will start operation before waiting time completion. 5.3.4 standby mode transition and pin states when a sleep instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, and bit tma3 is cleared to 0 in tma, a transition is made to standby mode. at the same time, pins go to the high- impedance state (except pins for which the pull-up mos is designated as on). figure 5.2 shows the timing in this case. section 5 power-down modes rev. 6.00 aug 04, 2006 page 132 of 626 rej09b0144-0600 sleep instruction fetch internal data bus fetch of next instruction port output pins high-impedance active (high-speed) mode or active (medium-speed) mode standby mode sleep instruction execution internal processing figure 5.2 standby mode transition and pin states 5.3.5 notes on external input signal changes before/after standby mode 1. when external input signal changes before/after standby mode or watch mode when an external input signal such as irq or wkp is input, both the high- and low-level widths of the signal must be at least two cycles of system clock or subclock sub (referred to together in this section as the internal clock). as the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. ensure that external input signals conform to the conditions stated in 3, recommended timing of external input signals, below 2. when external input signals cannot be captured because internal clock stops the case of falling edge capture is illustrated in figure 5.3 as shown in the case marked "capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 t cyc or 2 t subcyc . 3. recommended timing of external input signals to ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 t cyc or 2 t subcyc are necessary before a transition is made to standby mode or watch mode, as shown in "capture possible: case 1." external input signal capture is also possible with the timing shown in "capture possible: case 2" and "capture possible: case 3," in which a 2 t cyc or 2 t subcyc level width is secured. section 5 power-down modes rev. 6.00 aug 04, 2006 page 133 of 626 rej09b0144-0600 t cyc t subcyc operating mode or sub capture possible: case 1 capture possible: case 2 capture possible: case 3 capture not possible interrupt by different signall external input signal active (high-speed, medium-speed) mode or subactive mode active (high-speed, medium-speed) mode or subactive mode standby mode or watch mode wait for oscillation to settle t cyc t subcyc t cyc t subcyc t cyc t subcyc figure 5.3 external input signal capture when signal changes before/after standby mode or watch mode 4. input pins to which these notes apply: irq 4 to irq 0 , wkp 7 to wkp 0 , adtrg , tmic, tmif, tmig section 5 power-down modes rev. 6.00 aug 04, 2006 page 134 of 626 rej09b0144-0600 5.4 watch mode 5.4.1 transition to watch mode the system goes from active or subactive mode to watch mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1. in watch mode, operation of on-chip peripheral modules is halted except for timer a, timer f, timer g, aec and the lcd controller/driver (for which operation or halting can be set) is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules, are retained. i/o ports keep the same states as before the transition. 5.4.2 clearing watch mode watch mode is cleared by an interrupt (timer a, timer f, timer g, irq 0 , or wkp 7 to wkp 0 ) or by input at the res pin. ? clearing by interrupt when watch mode is cleared by interrupt, the mode to which a transition is made depends on the settings of lson in syscr1 and mson in syscr2. if both lson and mson are cleared to 0, transition is to active (high-speed) mode; if lson = 0 and mson = 1, transition is to active (medium-speed) mode; if lson = 1, transition is to subactive mode. when the transition is to active mode, after the time set in syscr1 bits sts2 to sts0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. watch mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. ? clearing by res input clearing by res pin is the same as for standby mode; see 2. clearing by res pin in section 5.3.2, clearing standby mode. 5.4.3 oscillator settling time after watch mode is cleared the waiting time is the same as for standby mode; see section 5.3.3, oscillator settling time after standby mode is cleared. section 5 power-down modes rev. 6.00 aug 04, 2006 page 135 of 626 rej09b0144-0600 5.4.4 notes on external input signal changes before/after watch mode see section 5.3.5, notes on external input signal changes before/after standby mode. 5.5 subsleep mode 5.5.1 transition to subsleep mode the system goes from subactive mode to subsleep mode when a sleep instruction is executed while the ssby bit in syscr1 is cleared to 0, lson bit in syscr1 is set to 1, and tma3 bit in tma is set to 1. in subsleep mode, operation of on-chip peripheral modules other than the a/d converter wdt and pwm is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. 5.5.2 clearing subsleep mode subsleep mode is cleared by an interrupt (timer a, timer c, timer f, timer g, asynchronous counter, sci3-2, sci3-1, irq 4 to irq 0 , wkp 7 to wkp 0 ) or by a low input at the res pin. ? clearing by interrupt when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. interrupt signal and system clock are mutually asynchronous. synchronization error time in a maximum is 2/ sub (s). ? clearing by res input clearing by res pin is the same as for standby mode; see 2. clearing by res pin in section 5.3.2, clearing standby mode. section 5 power-down modes rev. 6.00 aug 04, 2006 page 136 of 626 rej09b0144-0600 5.6 subactive mode 5.6.1 transition to subactive mode subactive mode is entered from watch mode if a timer a, timer f, timer g, irq 0 , or wkp 7 to wkp 0 interrupt is requested while the lson bit in syscr1 is set to 1. from subsleep mode, subactive mode is entered if a timer a, timer c, timer f, timer g, asynchronous counter, sci3-1, sci3-2, irq 4 to irq 0 , or wkp 7 to wkp 0 interrupt is requested. a transition to subactive mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 clearing subactive mode subactive mode is cleared by a sleep instruction or by a low input at the res pin. ? clearing by sleep instruction if a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and tma3 bit in tma is set to 1, subactive mode is cleared and watch mode is entered. if a sleep instruction is executed while ssby = 0 and lson = 1 in syscr1 and tma3 = 1 in tma, subsleep mode is entered. direct transfer to active mode is also possible; see section 5.8, direct transfer, below. ? clearing by res pin clearing by res pin is the same as for standby mode; see 2. clearing by res pin in section 5.3.2. 5.6.3 operating frequency in subactive mode the operating frequency in subactive mode is set in bits sa1 and sa0 in syscr2. the choices are w /2, w /4, and w /8. section 5 power-down modes rev. 6.00 aug 04, 2006 page 137 of 626 rej09b0144-0600 5.7 active (medium-speed) mode 5.7.1 transition to active (medium-speed) mode if the res pin is driven low, active (medium-speed) mode is entered. if the lson bit in syscr2 is set to 1 while the lson bit in syscr1 is cleared to 0, a transition to active (medium-speed) mode results from irq 0 , irq 1 , or wkp 7 to wkp 0 interrupts in standby mode, timer a, timer f, timer g, irq 0 , or wkp 7 to wkp 0 interrupts in watch mode, or any interrupt in sleep mode. a transition to active (medium-speed) mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. furthermore, it sometimes acts with half state early timing at the time of transition to active (medium-speed) mode. 5.7.2 clearing active (medium-speed) mode active (medium-speed) mode is cleared by a sleep instruction. ? clearing by sleep instruction a transition to standby mode takes place if the sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and the tma3 bit in tma is cleared to 0. the system goes to watch mode if the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1 when a sleep instruction is executed. when both ssby and lson are cleared to 0 in syscr1 and a sleep instruction is executed, sleep mode is entered. direct transfer to active (high-speed) mode or to subactive mode is also possible. see section 5.8, direct transfer, below for details. ? clearing by res pin when the res pin is driven low, a transition is made to the reset state and active (medium- speed) mode is cleared. 5.7.3 operating frequency in active (medium-speed) mode operation in active (medium-speed) mode is clocked at the frequency designated by the ma1 and ma0 bits in syscr1. section 5 power-down modes rev. 6.00 aug 04, 2006 page 138 of 626 rej09b0144-0600 5.8 direct transfer 5.8.1 overview of direct transfer the cpu can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. a direct transfer is a transition among these three modes without the stopping of program execution. a direct transfer can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. after the mode transition, direct transfer interrupt exception handling starts. if the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead to sleep mode or watch mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. ? direct transfer from active (high-speed) mode to active (medium-speed) mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. ? direct transfer from active (medium-speed) mode to active (high-speed) mode when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. ? direct transfer from active (high-speed) mode to subactive mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (high-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. section 5 power-down modes rev. 6.00 aug 04, 2006 page 139 of 626 rej09b0144-0600 ? direct transfer from active (medium-speed) mode to subactive mode when a sleep instruction is executed in active (medium-speed) while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (medium-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 5.8.2 direct transition times 1. time for direct transition from active (high-speed) mode to active (medium-speed) mode a direct transition from active (high-speed) mode to active (medium-speed) mode is performed by executing a sleep instruction in active (high-speed) mode while bits ssby and lson are both cleared to 0 in syscr1, and bits mson and dton are both set to 1 in syscr2. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (1) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition) .................................. (1) example: direct transition time = (2 + 1) 2tosc + 14 16tosc = 230tosc (when /8 is selected as the cpu operating clock) notation: tosc: osc clock cycle time tcyc: system clock ( ) cycle time section 5 power-down modes rev. 6.00 aug 04, 2006 page 140 of 626 rej09b0144-0600 2. time for direct transition from active (medium-speed) mode to active (high-speed) mode a direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a sleep instruction in active (medium-speed) mode while bits ssby and lson are both cleared to 0 in syscr1, and bit mson is cleared to 0 and bit dton is set to 1 in syscr2. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (2) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition) .................................. (2) example: direct transition time = (2 + 1) 16tosc + 14 2tosc = 76tosc (when /8 is selected as the cpu operating clock) notation: tosc: osc clock cycle time tcyc: system clock ( ) cycle time 3. time for direct transition from subactive mode to active (high-speed) mode a direct transition from subactive mode to active (high-speed) mode is performed by executing a sleep instruction in subactive mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, bit mson is cleared to 0 and bit dton is set to 1 in syscr2, and bit tma3 is set to 1 in tma. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (3) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tsubcyc before transition) + { (wait time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (tcyc after transition) ........................ (3) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 2tosc = 24tw + 16412tosc (when w/8 is selected as the cpu operating clock, and wait time = 8192 states) notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time section 5 power-down modes rev. 6.00 aug 04, 2006 page 141 of 626 rej09b0144-0600 4. time for direct transition from subactive mode to active (medium-speed) mode a direct transition from subactive mode to active (medium-speed) mode is performed by executing a sleep instruction in subactive mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, bits mson and dton are both set to 1 in syscr2, and bit tma3 is set to 1 in tma. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (4) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tsubcyc before transition) + { (wait time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (tcyc after transition) ........................ (4) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 16tosc = 24tw + 131296tosc (when w/8 or 8 is selected as the cpu operating clock, and wait time = 8192 states) notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time 5.8.3 notes on external input signal changes before/after direct transition 1. direct transition from active (high-speed) mode to subactive mode since the mode transition is performed via watch mode, see section 5.3.5, notes on external input signal changes before/after standby mode. 2. direct transition from active (medium-speed) mode to subactive mode since the mode transition is performed via watch mode, see section 5.3.5, notes on external input signal changes before/after standby mode. 3. direct transition from subactive mode to active (high-speed) mode since the mode transition is performed via watch mode, see section 5.3.5, notes on external input signal changes before/after standby mode. 4. direct transition from subactive mode to active (medium-speed) mode since the mode transition is performed via watch mode, see section 5.3.5, notes on external input signal changes before/after standby mode. section 5 power-down modes rev. 6.00 aug 04, 2006 page 142 of 626 rej09b0144-0600 5.9 module standby mode 5.9.1 setting module standby mode module standby mode is set for individual peripheral functions. all the on-chip peripheral modules can be placed in module standby mode. when a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. this state is identical to standby mode. module standby mode is set for a particular module by setting the corresponding bit to 0 in clock stop register 1 (ckstpr1) or clock stop register 2 (ckstpr2). (see table 5.5.) 5.9.2 clearing module standby mode module standby mode is cleared for a particular module by setting the corresponding bit to 1 in clock stop register 1 (ckstpr1) or clock stop register 2 (ckstpr2). (see table 5.5.) following a reset, clock stop register 1 (ckstpr1) and clock stop register 2 (ckstpr2) are both initialized to h'ff. section 5 power-down modes rev. 6.00 aug 04, 2006 page 143 of 626 rej09b0144-0600 table 5.5 setting and clearing module standby mode by clock stop register register name bit name operation ckstpr1 tackstp 1 timer a module standby mode is cleared 0 timer a is set to module standby mode tcckstp 1 timer c module standby mode is cleared 0 timer c is set to module standby mode tfckstp 1 timer f module standby mode is cleared 0 timer f is set to module standby mode tgckstp 1 timer g module standby mode is cleared 0 timer g is set to module standby mode adckstp 1 a/d converter module standby mode is cleared 0 a/d converter is set to module standby mode s32ckstp 1 sci3-2 module standby mode is cleared 0 sci3-2 is set to module standby mode s31ckstp 1 sci3-1 module standby mode is cleared 0 sci3-1 is set to module standby mode ckstpr2 ldckstp 1 lcd module standby mode is cleared 0 lcd is set to module standby mode pwckstp 1 pwm module standby mode is cleared 0 pwm is set to module standby mode wdckstp 1 watchdog timer module standby mode is cleared 0 watchdog timer is set to module standby mode aeckstp 1 asynchronous event counter module standby mode is cleared 0 asynchronous event counter is set to module standby mode note: for details of module operation, see the sections on the individual modules. section 5 power-down modes rev. 6.00 aug 04, 2006 page 144 of 626 rej09b0144-0600 5.9.3 usage note if, due to the timing with which a peripheral module issues interrupt requests, the module in question is set to module standby mode before an interrupt is processed, the module will stop with the interrupt request still pending. in this situation, interrupt processing will be repeated indefinitely unless interrupts are prohibited. it is therefore necessary to ensure that no interrupts are generated when a module is set to module standby mode. the surest way to do this is to specify the module standby mode setting only when interrupts are prohibited (interrupts prohibited using the interrupt enable register or interrupts masked using bit ccr-i). section 6 rom rev. 6.00 aug 04, 2006 page 145 of 626 rej09b0144-0600 section 6 rom 6.1 overview the h8/3822r, h8/38322, and h8/38422 have 16 kbytes of on-chip mask rom, the h8/3823r, h8/38323, and h8/38423 have 24 kbytes, the h8/3824r, h8/3824s, h8/38324, and h8/38424 have 32 kbytes, the h8/3825r, h8/3825s, h8/38325, and h8/38425 have 40 kbytes, the h8/3826r, h8/3826s, h8/38326, and h8/38426 have 48 kbytes, and the h8/3827r, h8/3827s, h8/38327, and h8/38427 have 60 kbytes. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. the h8/3827r has a ztat? version with 60-kbyte prom. the h8/3827s group does not have a ztat? version. the h8/3827r ztat? version must be used. the f-ztat? versions of the h8/38327 and h8/38427 are equipped with 60 kbytes of flash memory. the f-ztat? versions of the h8/38324 and h8/38424 are equipped with 32 kbytes of flash memory. 6.1.1 block diagram figure 6.1 shows a block diagram of the on-chip rom. h'7ffe h'7fff internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'7ffe h'0002 h'0000 h'0000 h'0002 h'0001 h'0003 on-chip rom figure 6.1 rom block diagram (h8/3824r, h8/3824s, h8/38324, and h8/38424) section 6 rom rev. 6.00 aug 04, 2006 page 146 of 626 rej09b0144-0600 6.2 h8/3827r prom mode 6.2.1 setting to prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcontroller and allows the prom to be programmed in the same way as the standard hn27c101 eprom. however, page programming is not supported. table 6.1 shows how to set the chip to prom mode. table 6.1 setting to prom mode pin name setting test high level pb 4 /an 4 low level pb 5 /an 5 pb 6 /an 6 high level 6.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 32 pins, as listed in table 6.2. figure 6.2 shows the pin-to-pin wiring of the socket adapter. figure 6.3 shows a memory map. table 6.2 socket adapter package socket adapters (manufacturer) 80-pin (fp-80b) me3867esfs1h (minato) h7386bq080d3201 (data-i/o) 80-pin (fp-80a) me3867eshs1h (minato) h7386aq080d3201 (data-i/o) 80-pin (tfp-80c) me3867esns1h (minato) h7386ct080d3201 (data-i/o) section 6 rom rev. 6.00 aug 04, 2006 page 147 of 626 rej09b0144-0600 fp-80a , tfp-80c fp-80b pin 9 45 46 47 48 49 50 51 52 68 67 66 65 64 63 62 61 53 72 55 56 57 58 59 14 15 60 54 13 32, 26 73 8 3 80 11 12 16 5, 27 2 78 79 11 47 48 49 50 51 52 53 54 70 69 68 67 66 65 64 63 55 74 57 58 59 60 61 16 17 62 56 15 34, 28 75 10 5 2 13 14 18 7, 29 4 80 1 hn27c101 (32-pin) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 res p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 0 p4 3 p7 2 p7 3 p7 4 p7 5 p7 6 p1 4 p1 5 p7 7 p7 1 p1 3 v cc , cv cc av cc test x 1 pb 6 p1 1 p1 2 p1 6 v ss av ss pb 4 pb 5 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ea 15 ea 16 ce oe pgm v cc v ss note: pins not indicated in the figure should be left open. h8/3827r eprom socket figure 6.2 socket adapter pin correspondence (with hn27c101) section 6 rom rev. 6.00 aug 04, 2006 page 148 of 626 rej09b0144-0600 address in mcu mode address in prom mode h'0000 h'0000 h'1ffff h'edff h'edff on-chip prom uninstalled area * the output data is not guaranteed if this address area is read in prom mode. therefore, when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if programming is inadvertently performed from h'ee00 onward, it may not be possible to continue prom programming and verification. when programming, h'ff should be set as the data in this address area (h'ee00 to h'1ffff). note: * figure 6.3 h8/3827r memory map in prom mode section 6 rom rev. 6.00 aug 04, 2006 page 149 of 626 rej09b0144-0600 6.3 h8/3827r programming the write, verify, and other modes are selected as shown in table 6.3 in h8/3827r prom mode. table 6.3 mode selection in prom mode (h8/3827r) pins mode ce ce ce ce oe oe oe oe pgm pgm pgm pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write l h l v pp v cc data input address input verify l l h v pp v cc data output address input programming l l l v pp v cc high impedance address input disabled l h h hl l hhh notation l: low level h: high level v pp :v pp level v cc :v cc level the specifications for writing and reading are identical to those for the standard hn27c101 eprom. however, page programming is not supported, and so page programming mode must not be set. a prom programmer that only supports page programming mode cannot be used. when selecting a prom programmer, ensure that it supports high-speed, high-reliability byte-by-byte programming. also, be sure to specify addresses from h'0000 to h'edff. 6.3.1 writing and verifying an efficient, high-speed, high-reliability method is available for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. the basic flow of this high-speed, high-reliability programming method is shown in figure 6.4. section 6 rom rev. 6.00 aug 04, 2006 page 150 of 626 rej09b0144-0600 start set write/verify mode v = 6.0 v 0.25 v, v = 12.5 v 0.3 v cc pp address = 0 n = 0 n + 1 n pw verify write time t = 0.2n ms opw last address? set read mode v = 5.0 v 0.25 v, v = v cc pp cc read all addresses? end error n 25 < address + 1 address no yes no go go yes no no go go write time t = 0.2 ms 5% figure 6.4 high-speed, high-reliability programming flow chart section 6 rom rev. 6.00 aug 04, 2006 page 151 of 626 rej09b0144-0600 tables 6.4 and 6.5 give the electrical characteristics in programming mode. table 6.4 dc characteristics conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min typ max unit test condition input high- level voltage eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm v ih 2.4 ? v cc + 0.3 v input low- level voltage eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm v il ?0.3 ? 0.8 v output high- level voltage eo 7 to eo 0 v oh 2.4 ? ? v i oh = ?200 a output low- level voltage eo 7 to eo 0 v ol ? ? 0.45 v i ol = 0.8 ma input leakage current eo 7 to eo 0 , ea 16 to ea 0 oe , ce , pgm |il i |??2 av in = 5.25 v/ 0.5 v v cc current i cc ??40 ma v pp current i pp ??40 ma section 6 rom rev. 6.00 aug 04, 2006 page 152 of 626 rej09b0144-0600 table 6.5 ac characteristics conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25c 5c item symbol min typ max unit test condition address setup time t as 2 ? ? s figure 6.5 * 1 oe setup time t oes 2 ??s data setup time t ds 2 ??s address hold time t ah 0 ??s data hold time t dh 2 ??s data output disable time t df * 2 ? ? 130 ns v pp setup time t vps 2 ??s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite programming t opw * 3 0.19 ? 5.25 ms ce setup time t ces 2 ??s v cc setup time t vcs 2 ??s data output delay time t oe 0 ? 200 ns notes: 1. input pulse level: 0.45 v to 2.2 v input rise time/fall time 20 ns timingreference levels input: 0.8 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined at the point at which the output is floating and the output level cannot be read. 3. t opw is defined by the value given in figure 6.4, high-speed, high-reliability programming flow chart. section 6 rom rev. 6.00 aug 04, 2006 page 153 of 626 rej09b0144-0600 figure 6.5 shows a prom write/verify timing diagram. write input data output data verify address data v pp v pp t as t ah t ds t dh t df t oe t oes t pw t opw * t vps t vcs t ces v cc v cc ce pgm oe v cc +1 v cc note: * t opw is defined by the value shown in figure 6.4, high-speed, high-reliability programming flowchart. figure 6.5 prom write/verify timing section 6 rom rev. 6.00 aug 04, 2006 page 154 of 626 rej09b0144-0600 6.3.2 programming precautions ? use the specified programming voltage and timing. the programming voltage in prom mode (v pp ) is 12.5 v. use of a higher voltage can permanently damage the chip. be especially careful with respect to prom programmer overshoot. setting the prom programmer to renesas specifications for the hn27c101 will result in correct v pp of 12.5 v. ? make sure the index marks on the prom programmer socket, socket adapter, and chip are properly aligned. if they are not, the chip may be destroyed by excessive current flow. before programming, be sure that the chip is properly mounted in the prom programmer. ? avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. ? take care when setting the programming mode, as page programming is not supported. ? when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if programming is inadvertently performed from h'ee00 onward, it may not be possible to continue prom programming and verification. when programming, h'ff should be set as the data in address area h'ee00 to h'1ffff. section 6 rom rev. 6.00 aug 04, 2006 page 155 of 626 rej09b0144-0600 6.4 reliability of programmed data a highly effective way to improve data retention characteristics is to bake the programmed chips at 150c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 6.6 shows the recommended screening procedure. program chip and verify programmed data bake chip for 24 to 48 hours at 125 c to 150 c with power off read and check program install figure 6.6 recommended screening procedure if a series of programming errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects. please inform renesas technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking. section 6 rom rev. 6.00 aug 04, 2006 page 156 of 626 rej09b0144-0600 6.5 flash memory overview 6.5.1 features the features of the 60 kbytes or 32 kbytes of flash memory built into the f-ztat versions are summarized below. ? programming/erase methods ? the 60-kbyte flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory is configured as follows: 1 kbyte 4 blocks, 28 kbytes 1 block, 16 kbytes 1 block, 8 kbytes 1 block, 4 kbytes 1 block. the 32-kbyte flash memory is configured as follows: 1 kbyte 4 blocks, 28 kbytes 1 block. to erase the entire flash memory, each block must be erased in turn. ? reprogramming capability ? the flash memory can be reprogrammed up to 1,000 times. ? on-board programming ? on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? programmer mode ? flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? automatic bit rate adjustment ? for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection ? sets software protection against flash memory programming/erasing. ? power-down mode ? the power supply circuit is partly halted in the subactive mode and can be read in the power-down mode. section 6 rom rev. 6.00 aug 04, 2006 page 157 of 626 rej09b0144-0600 6.5.2 block diagram internal address bus module bus internal data bus (16 bits) flmcr1 bus interface/controller operating mode tes pin p32 pin p86 pin legend: flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr: erase block register flpwcr: flash memory power control register fenr: flash memory enable register flmcr2 ebr flpwcr fenr flash memory figure 6.7 block diagram of flash memory 6.5.3 block configuration figure 6.8 shows the block configuration of flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 1 kbyte 4 blocks, 28 kbytes 1 block, 16 kbytes 1 block, 8 kbytes 1 block, and 4 kbytes 1 block. erasing is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. section 6 rom rev. 6.00 aug 04, 2006 page 158 of 626 rej09b0144-0600 h'007f h'0000 h'0001 h'0002 h'00ff h'0080 h'0081 h'0082 h'03ff h'0380 h'0381 h'0382 h'047f h'0400 h'0401 h'0402 h'04ff h'0480 h'0481 h'0482 h'07ff h'0780 h'0781 h'0782 h'087f h'0800 h'0801 h'0802 h'080f h'0880 h'0881 h'0882 h'0bff h'0b80 h'0b81 h'0b82 h'0c7f h'0c00 h'0c01 h'0c02 h'0cff h'0c80 h'0c81 h'0c82 h'0fff h'0f80 h'0f81 h'0f82 h'107f h'1000 h'1001 h'1002 h'10ff h'1080 h'1081 h'1082 h'efff h'ef80 h'ef81 h'ef82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes erase unit 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 28 kbytes h'7fff h'7f80 h'7f81 h'7f82 h'807f h'8000 h'8001 h'8002 h'8cff h'8080 h'8081 h'8082 programming unit: 128 bytes erase unit 16 kbytes h'bfff h'bf80 h'bf81 h'bf82 h'c07f h'c000 h'c001 h'c002 h'ccff h'c080 h'c081 h'c082 programming unit: 128 bytes erase unit 8 kbytes h'dfff h'df80 h'df81 h'df82 h'e07f h'e000 h'e001 h'e002 h'ecff h'e080 h'e081 h'e082 programming unit: 128 bytes erase unit 4 kbytes figure 6.8 flash memory block configuration section 6 rom rev. 6.00 aug 04, 2006 page 159 of 626 rej09b0144-0600 6.5.4 register configuration table 6.6 lists the register configuration to control the flash memory when the built in flash memory is effective. table 6.6 register configuration register name abbreviation r/w initial value address flash memory control register 1 flmcr1 r/w h'00 h'f020 flash memory control register 2 flmcr2 r h'00 h'f021 flash memory power control register flpwcr r/w h'00 h'f022 erase block register ebr r/w h'00 h'f023 flash memory enable register fenr r/w h'00 h'f02b note: flmcr1, flmcr2, flpwcr, ebr, and fenr are 8 bit registers. only byte access is enabled which are two-state access. these registers are dedicated to the product in which flash memory is included. the product in which prom or rom is included does not have these registers. when the corresponding address is read in these products, the value is undefined. a write is disabled. section 6 rom rev. 6.00 aug 04, 2006 page 160 of 626 rej09b0144-0600 6.6 descriptions of registers of the flash memory 6.6.1 flash memory control register 1 (flmcr1) bit 76543210 ? swe esu psu ev pv e p initial value00000000 read/write ? r/w r/w r/w r/w r/w r/w r/w flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 6.8, flash memory programming/erasing. by setting this register, the flash memory enters program mode, erase mode, program-verify mode, or erase-verify mode. read the data in the state that bits 6 to 0 of this register are cleared when using flash memory as normal built-in rom. bit 7?reserved this bit is always read as 0 and cannot be modified. bit 6?software write enable (swe) this bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to 0 and the ebr register are to be set). bit 6 swe description 0 programming/erasing is disabled. other flmcr1 register bits and all ebr bits cannot be set. (initial value) 1 flash memory programming/erasing is enabled. bit 5?erase setup (esu) this bit is to prepare for changing to erase mode. set this bit to 1 before setting the e bit to 1 in flmcr1 (do not set swe, psu, ev, pv, e, and p bits at the same time). bit 5 esu description 0 the erase setup state is cancelled (initial value) 1 the flash memory changes to the erase setup state. set this bit to 1 before setting the e bit to 1 in flmcr1. section 6 rom rev. 6.00 aug 04, 2006 page 161 of 626 rej09b0144-0600 bit 4?program setup (psu) this bit is to prepare for changing to program mode. set this bit to 1 before setting the p bit to 1 in flmcr1 (do not set swe, esu, ev, pv, e, and p bits at the same time). bit 4 psu description 0 the program setup state is cancelled (initial value) 1 the flash memory changes to the program setup state. set this bit to 1 before setting the p bit to 1 in flmcr1. bit 3?erase-verify (ev) this bit is to set changing to or cancelling erase-verify mode (do not set swe, esu, psu, pv, e, and p bits at the same time). bit 3 ev description 0 erase-verify mode is cancelled (initial value) 1 the flash memory changes to erase-verify mode bit 2?program-verify (pv) this bit is to set changing to or cancelling program-verify mode (do not set swe, esu, psu, ev, e, and p bits at the same time). bit 2 pv description 0 program-verify mode is cancelled (initial value) 1 the flash memory changes to program-verify mode bit 1?erase (e) this bit is to set changing to or cancelling erase mode (do not set swe, esu, psu, ev, pv, and p bits at the same time). section 6 rom rev. 6.00 aug 04, 2006 page 162 of 626 rej09b0144-0600 bit 1 e description 0 erase mode is cancelled (initial value) 1 when this bit is set to 1, while the swe = 1 and esu = 1, the flash memory changes to erase mode. bit 0?program (p) this bit is to set changing to or cancelling program mode (do not set swe, esu, psu, ev, pv, and e bits at the same time). bit 0 p description 0 program mode is cancelled (initial value) 1 when this bit is set to 1, while the swe = 1 and psu = 1, the flash memory changes to program mode. 6.6.2 flash memory control register 2 (flmcr2) bit 76543210 fler??????? initial value00000000 read/write r ??????? flmcr2 is a register that displays the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit 7?flash memory error (fler) this bit is set when the flash memory detects an error and goes to the error-protection state during programming or erasing to the flash memory. see section 6.9.3, error protection, for details. bit 7 fler description 0 the flash memory operates normally. (initial value) 1 indicates that an error has occurred during an operation on flash memory (programming or erasing). section 6 rom rev. 6.00 aug 04, 2006 page 163 of 626 rej09b0144-0600 bits 6 to 0?reserved these bits are always read as 0 and cannot be modified. 6.6.3 erase block register (ebr) bit 76543210 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w ebr specifies the flash memory erase area block. ebr is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr to be automatically cleared to 0. when each bit is set to 1 in ebr, the corresponding block can be erased. other blocks change to the erase-protection state. see table 6.7 for the method of dividing blocks of the flash memory. when the whole bits are to be erased, erase them in turn in unit of a block. table 6.7 division of blocks to be erased ebr bit name block (size) address 0 eb0 eb0 (1 kbyte) h'0000 to h'03ff 1 eb1 eb1 (1 kbyte) h'0400 to h'07ff 2 eb2 eb2 (1 kbyte) h'0800 to h'0bff 3 eb3 eb3 (1 kbyte) h'0c00 to h'0fff 4 eb4 eb4 (28 kbytes) h'1000 to h'7fff 5 eb5 eb5 (16 kbytes) h'8000 to h'bfff 6 eb6 eb6 (8 kbytes) h'c000 to h'dfff 7 eb7 eb7 (4 kbytes) h'e000 to h'efff section 6 rom rev. 6.00 aug 04, 2006 page 164 of 626 rej09b0144-0600 6.6.4 flash memory power control register (flpwcr) bit 76543210 pdwnd??????? initial value00000000 read/write r/w ??????? flpwcr enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode. the power supply circuit can be read in the subactive mode, although it is partly halted in the power-down mode. bit 7?power-down disable (pdwnd) this bit selects the power-down mode of the flash memory when a transition to the subactive mode is made. bit 7 pdwnd description 0 when this bit is 0 and a transition is made to the subactive mode, the flash memory enters the power-down mode. (initial value) 1 when this bit is 1, the flash memory remains in the normal mode even after a transition is made to the subactive mode. bits 6 to 0?reserved these bits are always read as 0 and cannot be modified. section 6 rom rev. 6.00 aug 04, 2006 page 165 of 626 rej09b0144-0600 6.6.5 flash memory enable register (fenr) bit 76543210 flshe??????? initial value00000000 read/write r/w ??????? fenr controls cpu access to the flash memory control registers, flmcr1, flmcr2, ebr, and flpwcr. bit 7?flash memory control register enable (flshe) this bit controls access to the flash memory control registers. bit 7 flshe description 0 flash memory control registers cannot be accessed (initial value) 1 flash memory control registers can be accessed bits 6 to 0?reserved these bits are always read as 0 and cannot be modified. section 6 rom rev. 6.00 aug 04, 2006 page 166 of 626 rej09b0144-0600 6.7 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the test pin settings, p32 pin settings, and input level of each port, as shown in table 6.8. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci32. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 6.8 setting programming modes test p32 p86 pb0 pb1 pb2 lsi state after reset end 0 1 xxxxuser mode 0 0 1 xxxboot mode 1xx000programmer mode x: don?t care 6.7.1 boot mode table 6.9 shows the boot mode operations between reset end and branching to the programming control program. the device uses sci32 in the boot mode. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 6.8, flash memory programming/erasing. 2. sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. the inversion function of txd and rxd pins by the spcr register is set to ?not to be inverted,? so do not put the circuit for inverting a value between the host and this lsi. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then section 6 rom rev. 6.00 aug 04, 2006 page 167 of 626 rej09b0144-0600 calculates the bit rate of transmission from the host, and adjusts the sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initiate boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 6.10. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'f780 to h'feef is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control program, the chip terminates transfer operations by sci3 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd pin is high (pcr42 = 1, p42 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the test pin and p32 pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and p32 pin input levels in boot mode. section 6 rom rev. 6.00 aug 04, 2006 page 168 of 626 rej09b0144-0600 table 6.9 boot mode operation item host operation lsi operation branches to boot program at reset-start. processing contents processing contents bit rate adjustment flash memory erase continuously transmits data h'00 at specified bit rate. measures low-level period of receive data h'00. calculates bit rate and sets it in brr of sci3. transmits data h'00 to the host to indicate that the adjustment has ended. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) transmits data h'55 when data h'00 is received and no error occurs. transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program transfer of programming control program execution of programming control program transfer of programming control program (repeated for n times) echobacks the 2-byte received data to host. transmits 1-byte data h'aa to host. branches to programming control program transferred to on-chip ram and starts execution. echobacks received data to host and also transfers it to ram. table 6.10 oscillating frequencies (f osc ) for which automatic adjustment of lsi bit rate is possible product group host bit rate oscillating frequencie s (f osc ) range of lsi 19,200 bps 16 mhz 9,600 bps 8 to 16 mhz 4,800 bps 6 to 16 mhz 2,400 bps 2 to 16 mhz h8/38327f-ztat h8/38324f-ztat h8/38427f-ztat h8/38424f-ztat 1,200 bps 2 to 16 mhz section 6 rom rev. 6.00 aug 04, 2006 page 169 of 626 rej09b0144-0600 6.7.2 programming/erasing in user program mode the term user mode refers to the status when a user program is being executed. on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 6.9 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 6.8, flash memory programming/erasing. ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 6.9 programming/erasing flowchart example in user program mode 6.8 flash memory programming/erasing a software method using the cpu is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control section 6 rom rev. 6.00 aug 04, 2006 page 170 of 626 rej09b0144-0600 program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 6.8.1, program/program-verify and section 6.8.2, erase/erase-verify, respectively. 6.8.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 6.10 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 6.11, and additional programming data computation according to table 6.12. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. figure 6.12 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 1 bit is b'0. verify data can be read in word size from the address to which a dummy write was performed. 8. the maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. section 6 rom rev. 6.00 aug 04, 2006 page 171 of 626 rej09b0144-0600 start end of programming set swe bit in flmcr1 write pulse application subroutine wait 1 figure 6.10 program/program-verify flowchart section 6 rom rev. 6.00 aug 04, 2006 page 172 of 626 rej09b0144-0600 table 6.11 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 101 ? 1 1 1 remains in erased state table 6.12 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 6.13 programming time n (number of writes) programming time in additional programming comments 1 to 6 30 10 7 to 1,000 200 ? note: time shown in s. section 6 rom rev. 6.00 aug 04, 2006 page 173 of 626 rej09b0144-0600 6.8.2 erase/erase-verify when erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 1 bit is b'0. verify data can be read in word size from the address to which a dummy write was performed. 6. if the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is 100. 6.8.3 interrupt handling when programming/erasing flash memory all interrupts, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. section 6 rom rev. 6.00 aug 04, 2006 page 174 of 626 rej09b0144-0600 erase start set ebr enable wdt wait 1 figure 6.11 erase/erase-verify flowchart section 6 rom rev. 6.00 aug 04, 2006 page 175 of 626 rej09b0144-0600 6.9 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register (ebr) are initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. 6.9.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block register (ebr), erase protection can be set for individual blocks. when ebr is set to h'00, erase protection is set for all blocks. 6.9.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling excluding a reset during programming/erasing ? when a sleep instruction is executed during programming/erasing the flmcr1, flmcr2, and ebr settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered section 6 rom rev. 6.00 aug 04, 2006 page 176 of 626 rej09b0144-0600 by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a power-on reset. 6.10 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. use a prom programmer that supports the mcu device type with the on-chip renesas technology (former hitachi ltd.) 64-kbyte flash memory (f-ztat64v3). a 10-mhz input clock is required. for the conditions for transition to programmer mode, see table 6.8. 6.10.1 socket adapter the socket adapter converts the pin allocation of the f-ztat device to that of the discrete flash memory hn28f101. the address of the on-chip flash memory is h'0000 to h'efff. figure 6.12 shows a socket-adapter-pin correspondence diagram. 6.10.2 programmer mode commands the following commands are supported in programmer mode. ? memory read mode ? auto-program mode ? auto-erase mode ? status read mode status polling is used for auto-programming, auto-erasing, and status read modes. in status read mode, detailed internal information is output after the execution of auto-programming or auto- erasing. table 6.14 shows the sequence of each command. in auto-programming mode, 129 cycles are required since 128 bytes are written at the same time. in memory read mode, the number of cycles depends on the number of address write cycles (n). section 6 rom rev. 6.00 aug 04, 2006 page 177 of 626 rej09b0144-0600 table 6.14 command sequence in programmer mode 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read 1 + n write x h'00 read ra dout auto-program 129 write x h'40 write wa din auto-erase 2 write x h'20 write x h'20 status read 2 write x h'71 write x h'71 n: the number of address write cycles section 6 rom rev. 6.00 aug 04, 2006 page 178 of 626 rej09b0144-0600 f-ztat device fp-80a tfp-80c pin no. pin no. pin name pin name p71 p77 p12 p60 p61 p62 p63 p64 p65 p66 p67 p87 p86 p85 p84 p83 p82 p81 p80 p70 p42 p72 p73 p74 p75 p76 p43 cvcc, vcc avcc x1 test v1 p14 avss, vss vss pb0 pb1 pb2 osc1,osc2 res (open) hn28f101 (32 pins) 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 fwe a9 a16 a15 we i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 a0 a1 a2 a3 a4 a5 a6 a7 a8 oe a10 a11 a12 a13 a14 ce vcc vss 54 60 12 45 46 47 48 49 50 51 52 68 67 66 65 64 63 62 61 53 71 55 56 57 58 59 72 26, 32 73 3 8 30 14 2, 5 27 74 75 76 7, 6 9 power-on reset circuit oscillator circuit socket adapter (conversion to 32-pin arrangement) other than the above legend: fwe: flash-write enable i/o7 to i/o0: data input/output a16 to a0: address input ce : chip enable oe : output enable we : write enable note: the oscillation frequency of the oscillator circuit should be 10 mhz. figure 6.12 socket adapter pin correspondence diagram section 6 rom rev. 6.00 aug 04, 2006 page 179 of 626 rej09b0144-0600 6.10.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. once memory read mode has been entered, consecutive reads can be performed. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. after powering on, memory read mode is entered. 4. tables 6.15 to 6.17 show the ac characteristics. table 6.15 ac characteristics in transition to memory read mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 ? s figure 6.13 ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns ce oe ce a15 ? oe we i/o7 ? we . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 6.13 timing waveforms for memory read after memory write section 6 rom rev. 6.00 aug 04, 2006 page 180 of 626 rej09b0144-0600 table 6.16 ac characteristics in transition from memory read mode to another mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 ? s figure 6.14 ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns ce a15 ? oe we i/o7 ? we and oe at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh other mode command write memory read mode figure 6.14 timing waveforms in transition from memory read mode to another mode section 6 rom rev. 6.00 aug 04, 2006 page 181 of 626 rej09b0144-0600 table 6.17 ac characteristics in memory read mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes access time t acc ? 20 s figure 6.15 ce output delay time t ce ? 150 ns figure 6.16 oe output delay time t oe ? 150 ns output disable delay time t df ? 100 ns data output hold time t oh 5?ns ce a15 ? oe we i/o7 ? figure 6.15 ce ce ce ce and oe oe oe oe enable state read timing waveforms ce a15 ? oe we i/o7 ? figure 6.16 ce ce ce ce and oe oe oe oe clock system read timing waveforms section 6 rom rev. 6.00 aug 04, 2006 page 182 of 626 rej09b0144-0600 6.10.4 auto-program mode 1. when reprogramming previously programmed addresses, perform auto-erasing before auto- programming. 2. perform auto-programming once only on the same address block. it is not possible to program an address block that has already been programmed. 3. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 4. the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 5. memory address transfer is performed in the second cycle (figure 6.17). do not perform transfer after the third cycle. 6. do not perform a command write during a programming operation. 7. perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. 8. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end decision pin). 9. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . 10. table 6.18 shows the ac characteristics. section 6 rom rev. 6.00 aug 04, 2006 page 183 of 626 rej09b0144-0600 table 6.18 ac characteristics in auto-program mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 ? s figure 6.17 ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t wsts 1?ms status polling access time t spa ? 150 ns address setup time t as 0?ns address hold time t ah 60 ? ns memory write time t write 1 3000 ms we rise time t r ?30ns we fall time t f ?30ns ce a15 ? oe we i/o7 i/o6 i/o5 ? figure 6.17 auto-program mode timing waveforms section 6 rom rev. 6.00 aug 04, 2006 page 184 of 626 rej09b0144-0600 6.10.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end decision pin). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . 5. table 6.19 shows the ac characteristics. table 6.19 ac characteristics in auto-erase mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 ? s figure 6.18 ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t ests 1?ms status polling access time t spa ? 150 ns memory erase time t erase 100 40000 ms we rise time t r ?30ns we fall time t f ?30ns section 6 rom rev. 6.00 aug 04, 2006 page 185 of 626 rej09b0144-0600 ce a15 ? oe we i/o7 i/o6 i/o5 ? figure 6.18 auto-erase mode timing waveforms 6.10.6 status read mode 1. status read mode is provided to identify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than a status read mode command write is executed. 3. table 6.20 shows the ac characteristics and 6.21 shows the return codes. section 6 rom rev. 6.00 aug 04, 2006 page 186 of 626 rej09b0144-0600 table 6.20 ac characteristics in status read mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes read time after command write t nxtc 20 ? s figure 6.19 ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns oe output delay time t oe ? 150 ns disable delay time t df ? 100 ns ce output delay time t ce ? 150 ns we rise time t r ?30ns we fall time t f ?30ns ce a15 ? oe we i/o7 ? figure 6.19 status read mode timing waveforms section 6 rom rev. 6.00 aug 04, 2006 page 187 of 626 rej09b0144-0600 table 6.21 status read mode return codes pin name initial value indications i/o7 0 1: abnormal end 0: normal end i/o6 0 1: command error 0: otherwise i/o5 0 1: programming error 0: otherwise i/o4 0 1: erasing error 0: otherwise i/o3 0 ? i/o2 0 ? i/o1 0 1: over counting of writing or erasing 0: otherwise i/o0 0 1: effective address error 0: otherwise 6.10.7 status polling 1. the i/o7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. the i/o6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. table 6.22 status polling output truth table i/o7 i/o6 i/o0 to 5 status 0 0 0 during internal operation 1 0 0 abnormal end 1 1 0 normal end 010? section 6 rom rev. 6.00 aug 04, 2006 page 188 of 626 rej09b0144-0600 6.10.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 6.23 stipulated transition times to command wait state item symbol min max unit notes oscillation stabilization time(crystal oscillator) t osc1 10 ? ms figure 6.20 oscillation stabilization time(ceramic oscillator) t osc1 5?ms programmer mode setup time t bmv 10 ? ms vcc hold time t dwn 0?ms t osc1 t bmv t dwn vcc r es auto-program mode auto-erase mode figure 6.20 oscillation stabilization time, boot program transfer time, and power-down sequence 6.10.9 notes on memory programming 1. when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. 2. the flash memory is initially in the erased state when the device is shipped by renesas technology. for other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. section 6 rom rev. 6.00 aug 04, 2006 page 189 of 626 rej09b0144-0600 6.11 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read and written to at high speed. ? power-down operating mode the power supply circuit of the flash memory is partly halted and can be read under low power consumption. ? standby mode all flash memory circuits are halted. table 6.24 shows the correspondence between the operating modes of this lsi and the flash memory. in subactive mode, the flash memory can be set to operate in power-down mode with the pdwnd bit in flpwcr. when the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in syscr1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. table 6.24 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode standby mode standby mode standby mode watch mode standby mode standby mode section 6 rom rev. 6.00 aug 04, 2006 page 190 of 626 rej09b0144-0600 section 7 ram rev. 6.00 aug 04, 2006 page 191 of 626 rej09b0144-0600 section 7 ram 7.1 overview the h8/3822r, h8/3823r, h8/38322, h8/38323, h8/38422, and h8/38423 have 1 kbyte of high- speed static ram on-chip, and the h8/3824r, h8/3824s, h8/38324, h8/38424, h8/3825r, h8/3825s, h8/38325, h8/38425, h8/3826r, h8/3826s, h8/38326, h8/38426, h8/3827r, h8/3827s, h8/38327, and h8/38427 have 2 kbytes. the ram is connected to the cpu by a 16- bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 block diagram figure 7.1 shows a block diagram of the on-chip ram. h'ff7e h'ff7f internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'ff7e h'f782 h'f780 h'f780 h'f782 h'f781 h'f783 on-chip ram figure 7.1 ram block diagram (h8/3824r, h8/3824s, h8/38324, and h8/38424) section 7 ram rev. 6.00 aug 04, 2006 page 192 of 626 rej09b0144-0600 section 8 i/o ports rev. 6.00 aug 04, 2006 page 193 of 626 rej09b0144-0600 section 8 i/o ports 8.1 overview the h8/3827r group, h8/3827s group, and h8/38327 group is provided with six 8-bit i/o ports, one 4-bit i/o port, one 3-bit i/o port, one 8-bit input-only port, and one 1-bit input-only port. table 8.1 indicates the functions of each port. each port has of a port control register (pcr) that controls input and output, and a port data register (pdr) for storing output data. input or output can be assigned to individual bits. see section 2.9.2, notes on bit manipulation, for information on executing bit-manipulation instructions to write data in pcr or pdr. ports 5, 6, 7, 8, and a are also used as liquid crystal display segment and common pins, selectable in 8-bit units. block diagrams of each port are given in appendix c, i/o port block diagrams. table 8.1 port functions port description pins other functions function switching registers port 1 ? 8-bit i/o port ? mos input pull-up option p1 7 to p1 5 / irq 3 to irq 1 / tmif, tmic external interrupts 3 to 1 timer event interrupts tmif, tmic pmr1 tcrf, tmc p1 4 / irq 4 / adtrg external interrupt 4 and a/d converter external trigger pmr1, amr p1 3 /tmig timer g input capture input pmr1 p1 2 , p1 1 / tmofh, tmofl timer f output compare output pmr1 p1 0 /tmow timer a clock output pmr1 section 8 i/o ports rev. 6.00 aug 04, 2006 page 194 of 626 rej09b0144-0600 port description pins other functions function switching registers port 3 p3 7 /aevl p3 6 /aevh p3 5 /txd 31 p3 4 /rxd 31 p3 3 /sck 31 sci3-1 data output (txd 31 ), data input (rxd 31 ), clock input/output (sck 31 ), and asynchronous counter event inputs aevl, aevh pmr3 scr31 smr31 ? 8-bit i/o port ? mos input pull-up option ? large-current port (h8/3827r group, h8/38327 group and h8/38427 group) p3 2 / reso * 1 p3 1 /ud/excl * 2 p3 0 /pwm reset output * 1 , timer c count-up/down select input, 14-bit pwm output, and external subclock input * 2 pmr2 pmr3 port 4 p4 3 / irq 0 external interrupt 0 pmr3 ? 1-bit input port ? 3-bit i/o port p4 2 /txd 32 p4 1 /rxd 32 p4 0 /sck 32 sci3-2 data output (txd 32 ), data input (rxd 32 ), clock input/output (sck 32 ) scr32 smr32 port 5 ? 8-bit i/o port ? mos input pull-up option p5 7 to p5 0 / wkp 7 to wkp 0 / seg 8 to seg 1 wakeup input ( wkp 7 to wkp 0 ), segment output (seg 8 to seg 1 ) pmr5 lpcr port 6 ? 8-bit i/o port ? mos input pull-up option p6 7 to p6 0 / seg 16 to seg 9 segment output (seg 16 to seg 9 ) lpcr port 7 ? 8-bit i/o port p7 7 to p7 0 / seg 24 to seg 17 segment output (seg 24 to seg 17 ) lpcr port 8 ? 8-bit i/o port p8 7 /seg 32 /cl 1 * 3 p8 6 /seg 31 /cl 2 * 3 p8 5 /seg 30 /do * 3 p8 4 /seg 29 /m * 3 p8 3 to p8 0 / seg 28 to seg 25 segment output (seg 32 to seg 25 ) segment external expansion latch clock (cl 1 ) * 3 , shift clock (cl 2 ) * 3 , display data (do) * 3 , alternation signal (m) * 3 lpcr port a 4-bit i/o port pa 3 to pa 0 / com 4 to com 1 common output (com 4 to com 1 ) lpcr port b 8-bit input port pb 7 to pb 0 / an 7 to an 0 a/d converter analog input amr notes: 1. the reso function is not implemented in the h8/38327 group and h8/38427 group. 2. the excl function is only implemented in the h8/38327 group and h8/38427 group. 3. the external expansion function for lcd segments is not implemented in the h8/38327 group and h8/38427 group. section 8 i/o ports rev. 6.00 aug 04, 2006 page 195 of 626 rej09b0144-0600 8.2 port 1 8.2.1 overview port 1 is a 8-bit i/o port. figure 8.1 shows its pin configuration. p1 / irq /tmif p1 / irq p1 / irq /tmic p1 / irq / adtr g p1 /tmig 7 6 5 4 3 3 2 1 4 port 1 p1 /tmofh p1 /tmofl p1 /tmow 2 1 0 figure 8.1 port 1 pin configuration 8.2.2 register configuration and description table 8.2 shows the port 1 register configuration. table 8.2 port 1 registers name abbr. r/w initial value address port data register 1 pdr1 r/w h'00 h'ffd4 port control register 1 pcr1 w h'00 h'ffe4 port pull-up control register 1 pucr1 r/w h'00 h'ffe0 port mode register 1 pmr1 r/w h'00 h'ffc8 section 8 i/o ports rev. 6.00 aug 04, 2006 page 196 of 626 rej09b0144-0600 1. port data register 1 (pdr1) bit initial value read/write 7 p1 0 r/w 6 p1 0 r/w 5 p1 0 r/w 4 p1 0 r/w 3 p1 0 r/w 0 p1 0 r/w 2 p1 0 r/w 1 p1 0 r/w 76543210 pdr1 is an 8-bit register that stores data for port 1 pins p1 7 to p1 0 . if port 1 is read while pcr1 bits are set to 1, the values stored in pdr1 are read, regardless of the actual pin states. if port 1 is read while pcr1 bits are cleared to 0, the pin states are read. upon reset, pdr1 is initialized to h'00. 2. port control register 1 (pcr1) bit initial value read/write 7 pcr1 0 w 6 pcr1 0 w 5 pcr1 0 w 4 pcr1 0 w 3 pcr1 0 w 0 pcr1 0 w 2 pcr1 0 w 1 pcr1 0 w 76543210 pcr1 is an 8-bit register for controlling whether each of the port 1 pins p1 7 to p1 0 functions as an input pin or output pin. setting a pcr1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr1 and in pdr1 are valid only when the corresponding pin is designated in pmr1 as a general i/o pin. upon reset, pcr1 is initialized to h'00. pcr1 is a write-only register, which is always read as all 1s. section 8 i/o ports rev. 6.00 aug 04, 2006 page 197 of 626 rej09b0144-0600 3. port pull-up control register 1 (pucr1) bit initial value read/write 7 pucr1 0 r/w 6 pucr1 0 r/w 5 pucr1 0 r/w 4 pucr1 0 r/w 3 pucr1 0 r/w 0 pucr1 0 r/w 2 pucr1 0 r/w 1 pucr1 0 r/w 7 65 4 32 10 pucr1 controls whether the mos pull-up of each of the port 1 pins p1 7 to p1 0 is on or off. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr1 is initialized to h'00. 4. port mode register 1 (pmr1) bit initial value read/write 7 irq3 0 r/w 6 irq2 0 r/w 5 irq1 0 r/w 4 irq4 0 r/w 3 tmig 0 r/w 0 tmow 0 r/w 2 tmofh 0 r/w 1 tmofl 0 r/w pmr1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. upon reset, pmr1 is initialized to h'00. bit 7: p1 7 / irq 3 /tmif pin function switch (irq3) this bit selects whether pin p1 7 / irq 3 /tmif is used as p1 7 or as irq 3 /tmif. bit 7 irq3 description 0 functions as p1 7 i/o pin (initial value) 1 functions as irq 3 /tmif input pin note: rising or falling edge sensing can be designated for irq 3 , tmif. for details on tmif settings, see 3. timer control register f (tcrf) in section 9.4.2. section 8 i/o ports rev. 6.00 aug 04, 2006 page 198 of 626 rej09b0144-0600 bit 6: p1 6 / irq 2 pin function switch (irq2) this bit selects whether pin p1 6 / irq 2 is used as p1 6 or as irq 2 . bit 6 irq2 description 0 functions as p1 6 i/o pin (initial value) 1 functions as irq 2 input pin note: rising or falling edge sensing can be designated for irq 2 . bit 5: p1 5 / irq 1 /tmic pin function switch (irq1) this bit selects whether pin p1 5 / irq 1 /tmic is used as p1 5 or as irq 1 /tmic. bit 5 irq1 description 0 functions as p1 5 i/o pin (initial value) 1 functions as irq 1 /tmic input pin note: rising or falling edge sensing can be designated for irq 1 /tmic. for details of tmic pin setting, see 1. timer mode register c (tmc) in section 9.3.2. bit 4: p1 4 / irq 4 / adtrg pin function switch (irq4) this bit selects whether pin p1 4 / irq 4 / adtrg is used as p1 4 or as irq 4 / adtrg . bit 4 irq4 description 0 functions as p1 4 i/o pin (initial value) 1 functions as irq 4 / adtrg input pin note: for details of adtrg pin setting, see section 12.3.2, start of a/d conversion by external trigger input. section 8 i/o ports rev. 6.00 aug 04, 2006 page 199 of 626 rej09b0144-0600 bit 3: p1 3 /tmig pin function switch (tmig) this bit selects whether pin p1 3 /tmig is used as p1 3 or as tmig. bit 3 tmig description 0 functions as p1 3 i/o pin (initial value) 1 functions as tmig input pin bit 2: p1 2 /tmofh pin function switch (tmofh) this bit selects whether pin p1 2 /tmofh is used as p1 2 or as tmofh. bit 2 tmofh description 0 functions as p1 2 i/o pin (initial value) 1 functions as tmofh output pin bit 1: p1 1 /tmofl pin function switch (tmofl) this bit selects whether pin p1 1 /tmofl is used as p1 1 or as tmofl. bit 1 tmofl description 0 functions as p1 1 i/o pin (initial value) 1 functions as tmofl output pin bit 0: p1 0 /tmow pin function switch (tmow) this bit selects whether pin p1 0 /tmow is used as p1 0 or as tmow. bit 0 tmow description 0 functions as p1 0 i/o pin (initial value) 1 functions as tmow output pin section 8 i/o ports rev. 6.00 aug 04, 2006 page 200 of 626 rej09b0144-0600 8.2.3 pin functions table 8.3 shows the port 1 pin functions. table 8.3 port 1 pin functions pin pin functions and selection method p1 7 / irq 3 /tmif the pin function depends on bit irq3 in pmr1, bits cksl2 to cksl0 in tcrf, and bit pcr1 7 in pcr1. irq 3 01 pcr1 7 01 * cksl2 to cksl0 * not 0 ** 0 ** pin function p1 7 input pin p1 7 output pin irq 3 input pin irq 3 /tmif input pin note: when this pin is used as the tmif input pin, clear bit ien3 to 0 in ienr1 to disable the irq 3 interrupt. p1 6 / irq 2 the pin function depends on bits irq2 in pmr1 and bit pcr1 6 in pcr1. irq2 0 1 pcr1 6 01 * pin function p1 6 input pin p1 6 output pin irq 2 input pin p1 5 / irq 1 tmic the pin function depends on bit irq1 in pmr1, bits tmc2 to tmc0 in tmc, and bit pcr1 5 in pcr1. irq1 0 1 pcr1 5 01 * tmc2 to tmc0 * not 111 111 pin function p1 5 input pin p1 5 output pin irq 1 input pin irq 1 /tmic input pin note: when this pin is used as the tmic input pin, clear bit ien1 to 0 in ienr1 to disable the irq 1 interrupt. section 8 i/o ports rev. 6.00 aug 04, 2006 page 201 of 626 rej09b0144-0600 pin pin functions and selection method p1 4 / irq 4 adtrg the pin function depends on bit irq4 in pmr1, bit trge in amr, and bit pcr1 4 in pcr1. irq4 0 1 pcr1 4 01 * trge * 01 pin function p1 4 input pin p1 4 output pin irq 4 input pin irq 4 / adtrg input pin note: when this pin is used as the adtrg input pin, clear bit ien4 to 0 in ienr1 to disable the irq 4 interrupt. p1 3 /tmig the pin function depends on bit tmig in pmr1 and bit pcr1 3 in pcr1. tmig 0 1 pcr1 3 01 * pin function p1 3 input pin p1 3 output pin tmig input pin p1 2 /tmofh the pin function depends on bit tmofh in pmr1 and bit pcr1 2 in pcr1. tmofh 0 1 pcr1 2 01 * pin function p1 2 input pin p1 2 output pin tmofh output pin p1 1 /tmofl the pin function depends on bit tmofl in pmr1 and bit pcr1 1 in pcr1. tmofl 0 1 pcr1 1 01 * pin function p1 1 input pin p1 1 output pin tmofl output pin p1 0 /tmow the pin function depends on bit tmow in pmr1 and bit pcr1 0 in pcr1. tmow 0 1 pcr1 0 01 * pin function p1 0 input pin p1 0 output pin tmow output pin * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 202 of 626 rej09b0144-0600 8.2.4 pin states table 8.4 shows the port 1 pin states in each operating mode. table 8.4 port 1 pin states pins reset sleep subsleep standby watch subactive active p1 7 / irq 3 /tmif p1 6 / irq 2 p1 5 / irq 1 /tmic p1 4 / irq 4 / adtrg p1 3 /tmig p1 2 /tmofh p1 1 /tmofl p1 0 /tmow high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.2.5 mos input pull-up port 1 has a built-in mos input pull-up function that can be controlled by software. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset. pcr1 n 001 pucr1 n 01 * mos input pull-up off on off (n = 7 to 0) * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 203 of 626 rej09b0144-0600 8.3 port 3 8.3.1 overview port 3 is a 8-bit i/o port, configured as shown in figure 8.2. in the f-ztat version, the on-chip pull-up mos for pin p3 2 is on during the reset period. it turns off and normal operation resumes after the reset is cleared. this should be considered when making connections to external circuitry. note that in the mask rom and ztat versions p3 2 continues to operate normally. p3 /aevl p3 /aevh p3 /txd 7 6 5 port 3 31 p3 /rxd p3 /sck p3 / reso * 1 4 3 2 31 31 p3 /ud/excl * 2 p3 /pwm 1 0 notes: 1. the reso function is not implemented in the h8/38327 group and h8/38427 group. 2. the excl function only applies to the h8/38327 group and h8/38427 group. figure 8.2 port 3 pin configuration 8.3.2 register configuration and description table 8.5 shows the port 3 register configuration. table 8.5 port 3 registers name abbr. r/w initial value address port data register 3 pdr3 r/w h'00 h'ffd6 port control register 3 pcr3 w h'00 h'ffe6 port pull-up control register 3 pucr3 r/w h'00 h'ffe1 port mode register 2 pmr2 r/w h'58 h'ffc9 port mode register 3 pmr3 r/w h'04 h'ffca section 8 i/o ports rev. 6.00 aug 04, 2006 page 204 of 626 rej09b0144-0600 1. port data register 3 (pdr3) bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 r/w 2 p3 0 r/w 1 p3 0 r/w 210 54 76 3 pdr3 is an 8-bit register that stores data for port 3 pins p3 7 to p3 0 . if port 3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read, regardless of the actual pin states. if port 3 is read while pcr3 bits are cleared to 0, the pin states are read. upon reset, pdr3 is initialized to h'00. 2. port control register 3 (pcr3) bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 w 2 pcr3 0 w 1 pcr3 0 w 21 0 54 3 76 pcr3 is an 8-bit register for controlling whether each of the port 3 pins p3 7 to p3 0 functions as an input pin or output pin. setting a pcr3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr3 and in pdr3 are valid only when the corresponding pin is designated in pmr3 as a general i/o pin. upon reset, pcr3 is initialized to h'00. pcr3 is a write-only register, which is always read as all 1s. section 8 i/o ports rev. 6.00 aug 04, 2006 page 205 of 626 rej09b0144-0600 3. port pull-up control register 3 (pucr3) bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 2 10 5 43 76 pucr3 controls whether the mos pull-up of each of the port 3 pins p3 7 to p3 0 is on or off. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr3 is initialized to h'00. 4. port mode register 3 (pmr3) bit initial value read/write note: * the reso bit is not implemented in the h8/38327 group and h8/38427 group. 7 aevl 0 r/w 6 aevh 0 r/w 5 wdcks 0 r/w 4 ncs 0 r/w 3 irq0 0 r/w 0 pwm 0 r/w 2 reso * 1 r/w 1 ud 0 r/w pmr3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. upon reset, pmr3 is initialized to h'04. bit 7: p3 7 /aevl pin function switch (aevl) this bit selects whether pin p3 7 /aevl is used as p3 7 or as aevl. bit 7 aevl description 0 functions as p3 7 i/o pin (initial value) 1 functions as aevl input pin section 8 i/o ports rev. 6.00 aug 04, 2006 page 206 of 626 rej09b0144-0600 bit 6: p3 6 /aevh pin function switch (aevh) this bit selects whether pin p3 6 /aevh is used as p3 6 or as aevh. bit 6 aevh description 0 functions as p3 6 i/o pin (initial value) 1 functions as aevh input pin bit 5: watchdog timer source clock select (wdcks) this bit selects the watchdog timer source clock. bit 5 wdcks description 0 /8192 selected (initial value) 1 w/32 selected bit 4: tmig noise canceler select (ncs) this bit controls the noise canceler for the input capture input signal (tmig). bit 4 ncs description 0 noise cancellation function not used (initial value) 1 noise cancellation function used bit 3: p4 3 / irq 0 pin function switch (irq 0 ) this bit selects whether pin p4 3 / irq 0 is used as p4 3 or as irq 0 . bit 3 irq 0 description 0 functions as p4 3 input pin (initial value) 1 functions as irq 0 input pin section 8 i/o ports rev. 6.00 aug 04, 2006 page 207 of 626 rej09b0144-0600 bit 2: p3 2 / reso pin function switch (reso) this bit selects whether pin p3 2 / reso is used as p3 2 or as reso . in the h8/38327 group and h8/38427 group these bits are reserved and cannot be written to. bit 2 reso description 0 functions as p3 2 i/o pin 1 functions as reso output pin (initial value) bit 1: p3 1 /ud pin function switch (si1) this bit selects whether pin p3 1 /ud is used as p3 1 or as ud. bit 1 ud description 0 functions as p3 1 i/o pin (initial value) 1 functions as ud input pin bit 0: p3 0 /pwm pin function switch (pwm) this bit selects whether pin p3 0 /pwm is used as p3 0 or as pwm. bit 0 pwm description 0 functions as p3 0 i/o pin (initial value) 1 functions as pwm output pin section 8 i/o ports rev. 6.00 aug 04, 2006 page 208 of 626 rej09b0144-0600 5. port mode register 2 (pmr2) bit initial value read/write 7 excl 0 r/w 6 ? 1 r 5 ? 0 r/w 4 ? 1 r 3 ? 1 r 0 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w pmr2 is an 8-bit read/write register that controls external clock input to pin p3 1 . upon reset, pmr2 is initialized to h'58. the information on this register applies to the h8/38327 group and h8/38427 group. bit 7: p3 1 /ud/excl pin function switch (excl) this bit selects whether pin p3 1 /ud/excl is used as p3 1 /ud or as excl. when the pin is used as excl an external clock should be input to it. see section 4, clock pulse generators, for a connection example. bit 7 excl description 0 functions as p3 1 /ud i/o pin (initial value) 1 functions as excl input pin bit 6: reserved bit bit 6 is a reserved bit. it is always read as 1 and cannot be modified. bit 5: reserved bit bit 5 is a readable/writable reserved bit. bits 4 and 3: reserved bits bits 4 and 3 are reserved bits. they are always read as 1 and cannot be modified. bits 2 to 0: reserved bits bits 2 to 0 are readable/writable reserved bits. section 8 i/o ports rev. 6.00 aug 04, 2006 page 209 of 626 rej09b0144-0600 8.3.3 pin functions table 8.6 shows the port 3 pin functions. table 8.6 port 3 pin functions pin pin functions and selection method p3 7 /aevl the pin function depends on bit so1 in pmr3 and bit pcr3 7 in pcr3. aevl 0 1 pcr3 7 01 * pin function p3 7 input pin p3 7 output pin aevl input pin p3 6 /aevh the pin function depends on bit aevh in pmr3 and bit pcr3 6 in pcr3. aevh 0 1 pcr3 6 01 * pin function p3 6 input pin p3 6 output pin aevh input pin p3 5 /txd 31 the pin function depends on bit te 31 in scr3-1, bit spc31 in spcr, and bit pcr3 5 in pcr3. spc31 0 1 te 31 01 pcr3 5 01 * pin function p3 5 input pin p3 5 output pin txd 31 output pin p3 4 /rxd 31 the pin function depends on bit re 31 in scr3-1 and bit pcr3 4 in pcr3. re 31 01 pcr3 4 01 * pin function p3 4 input pin p3 4 output pin rxd 31 input pin p3 3 /sck 31 the pin function depends on bits cke311, cke310, and smr31 in scr3-1 and bit pcr3 3 in pcr3. cke311 0 1 cke310 0 1 * com3 1 01 ** pcr3 3 01 ** pin function p3 3 input pin p3 3 output pin sck 31 output pin sck 31 input pin section 8 i/o ports rev. 6.00 aug 04, 2006 page 210 of 626 rej09b0144-0600 pin pin functions and selection method ? h8/3827r group and h8/3827s group the pin function depends on bit reso in pmr3 and bit pcr3 2 in pcr3. p3 2 / reso (h8/3827r, h8/3827s) reso 0 1 pcr3 2 01 * pin function p3 2 input pin p3 2 output pin reso output pin p3 2 (h8/38327, h8/38427) ? h8/38327 group and h8/38427 group the pin function depends on bit pcr3 2 in pcr3. pcr3 2 01 pin function p3 2 input pin p3 2 output pin ? h8/3827r group and h8/3827s group the pin function depends on bit ud in pmr3 and bit pcr3 1 in pcr3. ud 0 1 p3 1 /ud (h8/3827r, h8/3827s) pcr3 1 01 * pin function p3 1 input pin p3 1 output pin ud input pin p3 1 /ud/excl (h8/38327, h8/38427) ? h8/38327 group and h8/38427 group the pin function depends on bit excl in pmr2, bit ud in pmr3, and bit pcr3 1 in pcr3. excl 0 1 ud 0 1 * pcr3 1 0 1 ** pin function p3 1 input pin p3 1 output pin ud input pin excl input pin p3 0 /pwm the pin function depends on bit pwm in pmr3 and bit pcr3 0 in pcr3. pwm 0 1 pcr3 0 01 * pin function p3 0 input pin p3 0 output pin pwm output pin * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 211 of 626 rej09b0144-0600 8.3.4 pin states table 8.7 shows the port 3 pin states in each operating mode. table 8.7 port 3 pin states pins reset sleep subsleep standby watch subactive active p3 7 /aevl p3 6 /aevh p3 5 /txd 31 p3 4 /rxd 31 p3 3 /sck 31 high- impedance retains previous state retains previous state high- impedance * 1 retains previous state functional functional p3 2 / reso * 2 reso output p3 2 * 4 pull-up mos on p3 2 * 3 p3 1 /ud * 2 p3 1 /ud/excl * 3 * 4 p3 0 /pwm high- impedance notes: 1. a high-level signal is output when the mos pull-up is in the on state. 2. applies to h8/3827r group and h8/3827s group. 3. applies to the mask rom version of the h8/38327 group and h8/38427 group. 4. applies to the f-ztat version of the h8/38327 group and h8/38427 group. 8.3.5 mos input pull-up port 3 has a built-in mos input pull-up function that can be controlled by software. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr3 n 001 pucr3 n 01 * mos input pull-up off on off (n = 7 to 0) * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 212 of 626 rej09b0144-0600 8.4 port 4 8.4.1 overview port 4 is a 3-bit i/o port and 1-bit input port, configured as shown in figure 8.3. p4 p4 p4 p4 / irq 0 /txd 32 /rxd 32 /sck 32 3 2 1 0 port 4 figure 8.3 port 4 pin configuration 8.4.2 register configuration and description table 8.8 shows the port 4 register configuration. table 8.8 port 4 registers name abbr. r/w initial value address port data register 4 pdr4 r/w h'f8 h'ffd7 port control register 4 pcr4 w h'f8 h'ffe7 section 8 i/o ports rev. 6.00 aug 04, 2006 page 213 of 626 rej09b0144-0600 1. port data register 4 (pdr4) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 p4 1 r 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 321 0 pdr4 is an 8-bit register that stores data for port 4 pins p4 2 to p4 0 . if port 4 is read while pcr4 bits are set to 1, the values stored in pdr4 are read, regardless of the actual pin states. if port 4 is read while pcr4 bits are cleared to 0, the pin states are read. upon reset, pdr4 is initialized to h'f8. 2. port control register 4 (pcr4) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w 210 pcr4 is an 8-bit register for controlling whether each of port 4 pins p4 2 to p4 0 functions as an input pin or output pin. setting a pcr4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr4 and pdr4 settings are valid when the corresponding pins are designated for general-purpose input/output by scr3-2. upon reset, pcr4 is initialized to h'f8. pcr4 is a write-only register, which always reads all 1s. section 8 i/o ports rev. 6.00 aug 04, 2006 page 214 of 626 rej09b0144-0600 8.4.3 pin functions table 8.9 shows the port 4 pin functions. table 8.9 port 4 pin functions pin pin functions and selection method p4 3 / irq 0 the pin function depends on bit irq0 in pmr3. irq0 0 1 pin function p4 3 input pin irq 0 input pin p4 2 /txd 32 the pin function depends on bit te 32 in scr3-2, bit spc32 in spcr, and bit pcr4 2 in pcr4. spc32 0 1 te 32 01 pcr4 2 01 * pin function p4 2 input pin p4 2 output pin txd 32 output pin p4 1 /rxd 32 the pin function depends on bit re 32 in scr3-2 and bit pcr4 1 in pcr4. re 32 01 pcr4 1 01 * pin function p4 1 input pin p4 1 output pin rxd 32 input pin p4 0 /sck 32 the pin function depends on bit cke321 and cke320 in scr3-2, bit com32 in smr32, and bit pcr4 0 in pcr4. cke321 0 1 cke320 0 1 * com32 0 1 ** pcr4 0 01 ** pin function p4 0 input pin p4 0 output pin sck 32 output pin sck 32 input pin * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 215 of 626 rej09b0144-0600 8.4.4 pin states table 8.10 shows the port 4 pin states in each operating mode. table 8.10 port 4 pin states pins reset sleep subsleep standby watch subactive active p4 3 / irq 0 p4 2 /txd 32 p4 1 /rxd 32 p4 0 /sck 32 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 8.5 port 5 8.5.1 overview port 5 is an 8-bit i/o port, configured as shown in figure 8.4. p5 7 / wkp 7 /seg 8 p5 6 / wkp 6 /seg 7 p5 5 / wkp 5 /seg 6 p5 4 / wkp 4 /seg 5 p5 3 / wkp 3 /seg 4 p5 2 / wkp 2 /seg 3 p5 1 / wkp 1 /seg 2 p5 0 / wkp 0 /seg 1 port 5 figure 8.4 port 5 pin configuration section 8 i/o ports rev. 6.00 aug 04, 2006 page 216 of 626 rej09b0144-0600 8.5.2 register configuration and description table 8.11 shows the port 5 register configuration. table 8.11 port 5 registers name abbr. r/w initial value address port data register 5 pdr5 r/w h'00 h'ffd8 port control register 5 pcr5 w h'00 h'ffe8 port pull-up control register 5 pucr5 r/w h'00 h'ffe2 port mode register 5 pmr5 r/w h'00 h'ffcc 1. port data register 5 (pdr5) bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 76543210 pdr5 is an 8-bit register that stores data for port 5 pins p5 7 to p5 0 . if port 5 is read while pcr5 bits are set to 1, the values stored in pdr5 are read, regardless of the actual pin states. if port 5 is read while pcr5 bits are cleared to 0, the pin states are read. upon reset, pdr5 is initialized to h'00. 2. port control register 5 (pcr5) bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w 76543210 pcr5 is an 8-bit register for controlling whether each of the port 5 pins p5 7 to p5 0 functions as an input pin or output pin. setting a pcr5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr5 and pdr5 settings are valid when the corresponding pins are designated for general-purpose input/output by pmr5 and bits sgs3 to sgs0 in lpcr. upon reset, pcr5 is initialized to h'00. section 8 i/o ports rev. 6.00 aug 04, 2006 page 217 of 626 rej09b0144-0600 pcr5 is a write-only register, which is always read as all 1s. 3. port pull-up control register 5 (pucr5) bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 76543210 pucr5 controls whether the mos pull-up of each of port 5 pins p5 7 to p5 0 is on or off. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr5 is initialized to h'00. 4. port mode register 5 (pmr5) bit initial value read/write 7 wkp 7 0 r/w 6 wkp 6 0 r/w 5 wkp 5 0 r/w 4 wkp 4 0 r/w 3 wkp 3 0 r/w 0 wkp 0 0 r/w 2 wkp 2 0 r/w 1 wkp 1 0 r/w pmr5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. upon reset, pmr5 is initialized to h'00. bit n: p5 n / wkp n /seg n+1 pin function switch (wkpn) when pin p5n/ wkp n/segn+1 is not used as seg n+1 , these bits select whether the pin is used as p5n or wkp n . bit n wkpn description 0 functions as p5n i/o pin (initial value) 1 functions as wkp n input pin (n = 7 to 0) note: for use as seg n+1 , see section 13.2.1, lcd port control register (lpcr). section 8 i/o ports rev. 6.00 aug 04, 2006 page 218 of 626 rej09b0144-0600 8.5.3 pin functions table 8.12 shows the port 5 pin functions. table 8.12 port 5 pin functions pin pin functions and selection method the pin function depends on bit wkp n in pmr5, bit pcr5 n in pcr5, and bits sgs3 to sgs0 in lpcr. (n = 7 to 0) sgs3 to sgs0 0 *** 1 *** p5 7 / wkp 7 /seg 8 to p5 0 / wkp 0 /seg 1 wkp n 01 * pcr5 n 01 ** pin function p5 n input pin p5 n output pin wkp n input pin segn+1 output pin * : don?t care 8.5.4 pin states table 8.13 shows the port 5 pin states in each operating mode. table 8.13 port 5 pin states pins reset sleep subsleep standby watch subactive active p5 7 / wkp 7 / seg 8 to p5 0 / wkp 0 /seg 1 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. section 8 i/o ports rev. 6.00 aug 04, 2006 page 219 of 626 rej09b0144-0600 8.5.5 mos input pull-up port 5 has a built-in mos input pull-up function that can be controlled by software. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr5 n 001 pucr5 n 01 * mos input pull-up off on off (n = 7 to 0) * : don?t care 8.6 port 6 8.6.1 overview port 6 is an 8-bit i/o port. the port 6 pin configuration is shown in figure 8.5. p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 port 6 figure 8.5 port 6 pin configuration section 8 i/o ports rev. 6.00 aug 04, 2006 page 220 of 626 rej09b0144-0600 8.6.2 register configuration and description table 8.14 shows the port 6 register configuration. table 8.14 port 6 registers name abbr. r/w initial value address port data register 6 pdr6 r/w h'00 h'ffd9 port control register 6 pcr6 w h'00 h'ffe9 port pull-up control register 6 pucr6 r/w h'00 h'ffe3 1. port data register 6 (pdr6) bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 210 54 76 3 pdr6 is an 8-bit register that stores data for port 6 pins p6 7 to p6 0 . if port 6 is read while pcr6 bits are set to 1, the values stored in pdr6 are read, regardless of the actual pin states. if port 6 is read while pcr6 bits are cleared to 0, the pin states are read. upon reset, pdr6 is initialized to h'00. 2. port control register 6 (pcr6) bit initial value read/write 7 pcr6 7 0 w 6 pcr6 6 0 w 5 pcr6 5 0 w 4 pcr6 4 0 w 3 pcr6 3 0 w 0 pcr6 0 0 w 2 pcr6 2 0 w 1 pcr6 1 0 w pcr6 is an 8-bit register for controlling whether each of the port 6 pins p6 7 to p6 0 functions as an input pin or output pin. setting a pcr6 bit to 1 makes the corresponding pin (p6 7 to p6 0 ) an output pin, while clearing the bit to 0 makes the pin an input pin. pcr6 and pdr6 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr6 is initialized to h'00. section 8 i/o ports rev. 6.00 aug 04, 2006 page 221 of 626 rej09b0144-0600 pcr6 is a write-only register, which always reads all 1s. 3. port pull-up control register 6 (pucr6) bit initial value read/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 2 10 5 43 76 pucr6 controls whether the mos pull-up of each of the port 6 pins p6 7 to p6 0 is on or off. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr6 is initialized to h'00. 8.6.3 pin functions table 8.15 shows the port 6 pin functions. table 8.15 port 6 pin functions pin pin functions and selection method p6 7 /seg 16 to p6 0 /seg 9 the pin function depends on bit pcr6n in pcr6 and bits sgs3 to sgs0 in lpcr. (n = 7 to 0) seg3 to segs0 00 ** , 010 * 011 ** , 1 *** pcr6 n 01 * pin function p6 n input pin p6 n output pin seg n+9 output pin * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 222 of 626 rej09b0144-0600 8.6.4 pin states table 8.16 shows the port 6 pin states in each operating mode. table 8.16 port 6 pin states pin reset sleep subsleep standby watch subactive active p6 7 /seg 16 to p6 0 /seg 9 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.6.5 mos input pull-up port 6 has a built-in mos pull-up function that can be controlled by software. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr6 n 001 pucr6 n 01 * mos input pull-up off on off (n = 7 to 0) * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 223 of 626 rej09b0144-0600 8.7 port 7 8.7.1 overview port 7 is a 8-bit i/o port, configured as shown in figure 8.6. p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 port 7 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 figure 8.6 port 7 pin configuration 8.7.2 register configuration and description table 8.17 shows the port 7 register configuration. table 8.17 port 7 registers name abbr. r/w initial value address port data register 7 pdr7 r/w h'00 h'ffda port control register 7 pcr7 w h'00 h'ffea section 8 i/o ports rev. 6.00 aug 04, 2006 page 224 of 626 rej09b0144-0600 1. port data register 7 (pdr7) bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 76543210 pdr7 is an 8-bit register that stores data for port 7 pins p7 7 to p7 0 . if port 7 is read while pcr7 bits are set to 1, the values stored in pdr7 are read, regardless of the actual pin states. if port 7 is read while pcr7 bits are cleared to 0, the pin states are read. upon reset, pdr7 is initialized to h'00. 2. port control register 7 (pcr7) bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w 76543210 pcr7 is an 8-bit register for controlling whether each of the port 7 pins p7 7 to p7 0 functions as an input pin or output pin. setting a pcr7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr7 and pdr7 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr7 is initialized to h'00. pcr7 is a write-only register, which always reads as all 1s. section 8 i/o ports rev. 6.00 aug 04, 2006 page 225 of 626 rej09b0144-0600 8.7.3 pin functions table 8.18 shows the port 7 pin functions. table 8.18 port 7 pin functions pin pin functions and selection method p7 7 /seg 24 to p7 0 /seg 17 the pin function depends on bit pcr7 n in pcr7 and bits sgs3 to sgs0 in lpcr. (n = 7 to 0) segs3 to segs0 00 ** 01 ** , 1 *** pcr7 n 01 * pin function p7 n input pin p7 n output pin seg n+17 output pin * : don?t care 8.7.4 pin states table 8.19 shows the port 7 pin states in each operating mode. table 8.19 port 7 pin states pins reset sleep subsleep standby watch subactive active p7 7 /seg 24 to p7 0 /seg 17 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional section 8 i/o ports rev. 6.00 aug 04, 2006 page 226 of 626 rej09b0144-0600 8.8 port 8 8.8.1 overview port 8 is an 8-bit i/o port configured as shown in figure 8.7. p8 7 /seg 32 /cl 1 * p8 6 /seg 31 /cl 2 * p8 5 /seg 30 /do * p8 4 /seg 29 /m * p8 3 /seg 28 port 8 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 note: * the cl 1 , cl 2 , do, and m functions are not implemented on the h8/38327 group and h8/38427 group. figure 8.7 port 8 pin configuration 8.8.2 register configuration and description table 8.20 shows the port 8 register configuration. table 8.20 port 8 registers name abbr. r/w initial value address port data register 8 pdr8 r/w h'00 h'ffdb port control register 8 pcr8 w h'00 h'ffeb section 8 i/o ports rev. 6.00 aug 04, 2006 page 227 of 626 rej09b0144-0600 1. port data register 8 (pdr8) bit initial value read/write 7 p8 0 r/w 6 p8 0 r/w 5 p8 0 r/w 4 p8 0 r/w 3 p8 0 r/w 0 p8 0 r/w 2 p8 0 r/w 1 p8 0 r/w 76543210 pdr8 is an 8-bit register that stores data for port 8 pins p8 7 to p8 0 . if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are read, regardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. upon reset, pdr8 is initialized to h'00. 2. port control register 8 (pcr8) bit initial value read/write 7 pcr8 0 w 6 pcr8 0 w 5 pcr8 0 w 4 pcr8 0 w 3 pcr8 0 w 0 pcr8 0 w 2 pcr8 0 w 1 pcr8 0 w 76543210 pcr8 is an 8-bit register for controlling whether each of the port 8 pins p8 7 to p8 0 functions as an input or output pin. setting a pcr8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr8 and pdr8 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr8 is initialized to h'00. pcr8 is a write-only register, which is always read as all 1s. section 8 i/o ports rev. 6.00 aug 04, 2006 page 228 of 626 rej09b0144-0600 8.8.3 pin functions table 8.21 shows the port 8 pin functions. the sgx = 0 setting also functions on the h8/38327 and h8/38427. table 8.21 port 8 pin functions pin pin functions and selection method p8 7 /seg 32 / cl 1 the pin function depends on bit pcr8 7 in pcr8 and bits sgx and sgs3 to sgs0 in lpcr. segs3 to segs0 000 * 001 * , 01 ** , 1 *** 0000 sgx 0 0 1 pcr8 7 01 ** pin function p8 7 input pin p8 7 output pin seg 32 output pin cl 1 output pin p8 6 /seg 31 / cl 2 the pin function depends on bit pcr8 6 in pcr8 and bits sgx and sgs3 to sgs0 in lpcr. segs3 to segs0 000 * 001 * , 01 ** , 1 *** 0000 sgx 0 0 1 pcr8 6 01 ** pin function p8 6 input pin p8 6 output pin seg 31 output pin cl 2 output pin p8 5 /seg 30 / do the pin function depends on bit pcr8 5 in pcr8 and bits sgx and sgs3 to sgs0 in lpcr. segs3 to segs0 000 * 001 * , 01 ** , 1 *** 0000 sgx 0 0 1 pcr8 5 01 ** pin function p8 5 input pin p8 5 output pin seg 30 output pin d0 output pin p8 4 /seg 29 / m the pin function depends on bit pcr8 4 in pcr8 and bits sgx and sgs3 to sgs0 in lpcr. segs3 to segs0 000 * 001 * , 01 ** , 1 *** 0000 sgx 0 0 1 pcr8 4 01 ** pin function p8 4 input pin p8 4 output pin seg 29 output pin m output pin p8 3 /seg 28 to p8 0 /seg 25 the pin function depends on bit pcr8 n in pcr8 and bits sgs3 to sgs0 in lpcr. (n = 3 to 0) segs3 to segs0 000 * 001 * , 01 ** , 1 *** pcr8 n 01 * pin function p8 n input pin p8 n output pin seg n+25 output pin * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 229 of 626 rej09b0144-0600 8.8.4 pin states table 8.22 shows the port 8 pin states in each operating mode. table 8.22 port 8 pin states pins reset sleep subsleep standby watch subactive active p8 7 /seg 32 /cl 1 p8 6 /seg 31 /cl 2 p8 5 /seg 30 /do p8 4 /seg 29 /m p8 3 /seg 28 to p8 0 /seg 25 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 8.9 port a 8.9.1 overview port a is a 4-bit i/o port, configured as shown in figure 8.8. pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 port a figure 8.8 port a pin configuration section 8 i/o ports rev. 6.00 aug 04, 2006 page 230 of 626 rej09b0144-0600 8.9.2 register configuration and description table 8.23 shows the port a register configuration. table 8.23 port a registers name abbr. r/w initial value address port data register a pdra r/w h'f0 h'ffdd port control register a pcra w h'f0 h'ffed 1. port data register a (pdra) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 3210 pdra is an 8-bit register that stores data for port a pins pa 3 to pa 0 . if port a is read while pcra bits are set to 1, the values stored in pdra are read, regardless of the actual pin states. if port a is read while pcra bits are cleared to 0, the pin states are read. upon reset, pdra is initialized to h'f0. 2. port control register a (pcra) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 pcra 0 r/w 0 pcra 0 r/w 2 pcra 0 r/w 1 pcra 0 r/w 3210 pcra controls whether each of port a pins pa 3 to pa 0 functions as an input pin or output pin. setting a pcra bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcra and pdra settings are valid when the corresponding pins are designated for general-purpose input/output by lpcr. upon reset, pcra is initialized to h'f0. pcra is a write-only register, which always reads all 1s. section 8 i/o ports rev. 6.00 aug 04, 2006 page 231 of 626 rej09b0144-0600 8.9.3 pin functions table 8.24 shows the port a pin functions. table 8.24 port a pin functions pin pin functions and selection method pa 3 /com 4 the pin function depends on bit pcra 3 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 3 01 * pin function pa 3 input pin pa 3 output pin com 4 output pin pa 2 /com 3 the pin function depends on bit pcra 2 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 2 01 * pin function pa 2 input pin pa 2 output pin com 3 output pin pa 1 /com 2 the pin function depends on bit pcra 1 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 0000 not 0000 pcra 1 01 * pin function pa 1 input pin pa 1 output pin com 2 output pin pa 0 /com 1 the pin function depends on bit pcra 0 in pcra and bits sgs3 to sgs0. segs3 to segs0 0000 not 0000 pcra 0 01 * pin function pa 0 input pin pa 0 output pin com 1 output pin * : don?t care section 8 i/o ports rev. 6.00 aug 04, 2006 page 232 of 626 rej09b0144-0600 8.9.4 pin states table 8.25 shows the port a pin states in each operating mode. table 8.25 port a pin states pins reset sleep subsleep standby watch subactive active pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional 8.10 port b 8.10.1 overview port b is an 8-bit input-only port, configured as shown in figure 8.9. pb 7 /an 7 pb 6 /an 6 pb 5 /an 5 pb 4 /an 4 pb 3 /an 3 port b pb 2 /an 2 pb 1 /an 1 pb 0 /an 0 figure 8.9 port b pin configuration section 8 i/o ports rev. 6.00 aug 04, 2006 page 233 of 626 rej09b0144-0600 8.10.2 register configuration and description table 8.26 shows the port b register configuration. table 8.26 port b register name abbr. r/w address port data register b pdrb r h'ffde port data register b (pdrb) bit read/write 7 pb r 6 pb r 5 pb r 4 pb r 3 pb r 0 pb r 2 pb r 1 pb r 32 1 0 7654 reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel for the a/d converter by amr bits ch3 to ch0, that pin reads 0 regardless of the input voltage. 8.11 input/output data inversion function 8.11.1 overview with input pins wkp 0 to wkp 7 , rxd 31 , and rxd 32 , and output pins txd 31 and txd 32 , the data can be handled in inverted form. scinv0 scinv2 rxd 31 rxd 32 p3 4 /rxd 31 p4 1 /rxd 32 scinv1 scinv3 txd 31 txd 32 p3 5 /txd 31 p4 2 /txd 32 figure 8.10 input/output data inversion function section 8 i/o ports rev. 6.00 aug 04, 2006 page 234 of 626 rej09b0144-0600 8.11.2 register configuration and descriptions table 8.27 shows the registers used by the input/output data inversion function. table 8.27 register configuration name abbr. r/w address serial port control register spcr r/w h'ff91 serial port control register (spcr) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 spc32 0 r/w 4 spc31 0 r/w 3 scinv3 0 r/w 0 scinv0 0 r/w 2 scinv2 0 r/w 1 scinv1 0 r/w spcr is an 8-bit readable/writable register that performs rxd 31 , rxd 32 , txd 31 , and txd 32 pin input/output data inversion switching. spcr is initialized to h'c0 by a reset. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. bit 5: p4 2 /txd 32 pin function switch (spc32) this bit selects whether pin p4 2 /txd 32 is used as p4 2 or as txd 32 . bit 5 spc32 description 0 functions as p4 2 i/o pin (initial value) 1 functions as txd 32 output pin * note: * set the te bit in scr3 after setting this bit to 1. section 8 i/o ports rev. 6.00 aug 04, 2006 page 235 of 626 rej09b0144-0600 bit 4: p3 5 /txd 31 pin function switch (spc31) this bit selects whether pin p3 5 /txd 31 is used as p3 5 or as txd 31 . bit 4 spc31 description 0 functions as p3 5 i/o pin (initial value) 1 functions as txd 31 output pin * note: * set the te bit in scr3 after setting this bit to 1. bit 3: txd 32 pin output data inversion switch bit 3 specifies whether or not txd 32 pin output data is to be inverted. bit 3 scinv3 description 0txd 32 output data is not inverted (initial value) 1txd 32 output data is inverted bit 2: rxd 32 pin input data inversion switch bit 2 specifies whether or not rxd 32 pin input data is to be inverted. bit 2 scinv2 description 0rxd 32 input data is not inverted (initial value) 1rxd 32 input data is inverted bit 1: txd 31 pin output data inversion switch bit 1 specifies whether or not txd 31 pin output data is to be inverted. bit 1 scinv1 description 0txd 31 output data is not inverted (initial value) 1txd 31 output data is inverted section 8 i/o ports rev. 6.00 aug 04, 2006 page 236 of 626 rej09b0144-0600 bit 0: rxd 31 pin input data inversion switch bit 0 specifies whether or not rxd 31 pin input data is to be inverted. bit 0 scinv0 description 0rxd 31 input data is not inverted (initial value) 1rxd 31 input data is inverted 8.11.3 note on modification of serial port control register when a serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. when modifying a serial port control register, do so in a state in which data changes are invalidated. 8.12 application note 8.12.1 the management of the un-use terminal if an i/o pin not used by the user system is floating, pull it up or down. ? if an unused pin is an input pin, handle it in one of the following ways: ? pull it up to v cc with an on-chip pull-up mos. ? pull it up to v cc with an external resistor of approximately 100 k ? . ? pull it down to v ss with an external resistor of approximately 100 k ? . ? for a pin also used by the a/d converter, pull it up to av cc . ? if an unused pin is an output pin, handle it in one of the following ways: ? set the output of the unused pin to high and pull it up to v cc with an external resistor of approximately 100 k ? . ? set the output of the unused pin to low and pull it down to v ss with an external resistor of approximately 100 k ? . section 9 timers rev. 6.00 aug 04, 2006 page 237 of 626 rej09b0144-0600 section 9 timers 9.1 overview this lsi provides six timers: timers a, c, f, g, and a watchdog timer, and an asynchronous event counter. the functions of these timers are outlined in table 9.1. table 9.1 timer functions name functions internal clock event input pin waveform output pin remarks timer a ? 8-bit interval timer ? ? ? interval function /8 to /8192 (8 choices) ? time base w /128 (choice of 4 overflow periods) ? clock output /4 to /32 w , w /4 to w /32 (9 choices) ?tmow timer c ? 8-bit timer ? interval function ? event counting function ? up-count/down- count selectable /4 to /8192, w /4 (7 choices) tmic ? up-count/down- count controllable by software or hardware timer f 16-bit timer event counting function also usable as two independent8- bit timers output compare output function /4 to /32, w /4 (4 choices) tmif tmofl tmofh timer g ? 8-bit timer ? input capture function ? interval function /2 to /64, w /4 (4 choices) tmig ? ? counter clearing option ? built-in capture input signal noise canceler section 9 timers rev. 6.00 aug 04, 2006 page 238 of 626 rej09b0144-0600 name functions internal clock event input pin waveform output pin remarks watchdog timer ? reset signal generated when8-bit counter overflows /8192 w /32 ?? asynchro- nous event counter ? 16-bit counter ? also usable as two independent 8-bit counters ? counts events asynchronous to and w ? aevl aevh ? 9.2 timer a 9.2.1 overview timer a is an 8-bit timer with interval timing and real-time clock time-base functions. the clock time-base function is available when a 32.768-khz crystal oscillator is connected. a clock signal divided from 32.768 khz, from 38.4 khz (if a 38.4 khz crystal oscillator is connected), or from the system clock, can be output at the tmow pin. 1. features features of timer a are given below. ? choice of eight internal clock sources ( /8192, /4096, /2048, /512, /256, /128, /32, /8). ? choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer a is used as a clock time base (using a 32.768 khz crystal oscillator). ? an interrupt is requested when the counter overflows. ? any of nine clock signals can be output at the tmow pin: 32.768 khz divided by 32, 16, 8, or 4 (1 khz, 2 khz, 4 khz, 8 khz, 32,768 khz) or 38.4 khz divided by 32, 16, 8, or 4 (1.2 khz, 2.4 khz, 4.8 khz, 9.6 khz, 38.4 khz), and the system clock divided by 32, 16, 8, or 4. ? use of module standby mode enables this module to be placed in standby mode independently when not used. section 9 timers rev. 6.00 aug 04, 2006 page 239 of 626 rej09b0144-0600 2. block diagram figure 9.1 shows a block diagram of timer a. psw internal data bus pss legend: tmow 1/4 tma cwors tca w /32 w /16 w /8 w /4 /32 /16 /8 /4 /128 w /8192, /4096, /2048, /512, /256, /128, /32, /8 irrta 8 * 64 * 128 * 256 * /4 w tma: tca: irrta: psw: pss: cwosr: note: * can be selected only when the prescaler w output ( w /128) is used as the tca input clock. timer mode register a timer counter a timer a overflow interrupt request flag prescaler w prescaler s subclock output select register w figure 9.1 block diagram of timer a 3. pin configuration table 9.2 shows the timer a pin configuration. table 9.2 pin configuration name abbr. i/o function clock output tmow output output of waveform generated by timer a output circuit section 9 timers rev. 6.00 aug 04, 2006 page 240 of 626 rej09b0144-0600 4. register configuration table 9.3 shows the register configuration of timer a. table 9.3 timer a registers name abbr. r/w initial value address timer mode register a tma r/w h'10 h'ffb0 timer counter a tca r h'00 h'ffb1 clock stop register 1 ckstpr1 r/w h'ff h'fffa subclock output select register cwosr r/w h'fe h'ff92 9.2.2 register descriptions 1. timer mode register a (tma) bit initial value read/write 7 tma7 0 r/w 6 tma6 0 r/w 5 tma5 0 r/w 4 ? 1 ? 3 tma3 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w tma is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. upon reset, tma is initialized to h'10. section 9 timers rev. 6.00 aug 04, 2006 page 241 of 626 rej09b0144-0600 bits 7 to 5: clock output select (tma7 to tma5) bits 7 to 5 choose which of eight clock signals is output at the tmow pin. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz or 38.4 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. w is output in all modes except the reset state. cwosr tma cwos bit 7 tma7 bit 6 tma6 bit 5 tma5 clock output 0 000 /32 (initial value) 1 /16 10 /8 1 /4 100 w /32 1 w /16 10 w /8 1 w /4 1 *** w * : don?t care bit 4: reserved bit bit 4 is reserved; it is always read as 1, and cannot be modified. section 9 timers rev. 6.00 aug 04, 2006 page 242 of 626 rej09b0144-0600 bits 3 to 0: internal clock select (tma3 to tma0) bits 3 to 0 select the clock input to tca. the selection is made as follows. description bit 3 tma3 bit 2 tma2 bit 1 tma1 bit 0 tma0 prescaler and divider ratio or overflow period function 0000 pss, /8192 (initial value) interval timer 1 pss, /4096 1 0 pss, /2048 1 pss, /512 1 0 0 pss, /256 1 pss, /128 1 0 pss, /32 1 pss, /8 1000psw, 1 s 1 psw, 0.5 s 1 0 psw, 0.25 s 1 psw, 0.03125 s clock time base (when using 32.768 khz) 100psw and tca are reset 1 10 1 section 9 timers rev. 6.00 aug 04, 2006 page 243 of 626 rej09b0144-0600 2. timer counter a (tca) bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r tca is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in timer mode register a (tma). tca values can be read by the cpu in active mode, but cannot be read in subactive mode. when tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 of tma to 11. upon reset, tca is initialized to h'00. 3. clock stop register 1 (ckstpr1) ? tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer a is described here. for details of the other bits, see the sections on the relevant modules. bit 0: timer a module standby mode control (tackstp) bit 0 controls setting and clearing of module standby mode for timer a. tackstp description 0 timer a is set to module standby mode 1 timer a module standby mode is cleared (initial value) section 9 timers rev. 6.00 aug 04, 2006 page 244 of 626 rej09b0144-0600 4. subclock output select register (cwosr) ??? cwos ???? 76543210 1 1111110 r r r r/w rrr r bit initial value read/write cwosr is an 8-bit read/write register that selects the clock to be output from the tmow pin. cwosr is initialized to h'fe by a reset. bits 7 to 1: reserved bits bits 7 to 1 are reserved; they are always read as 1 and cannot be modified. bit 0: tmow pin clock select (cwos) bit 0 selects the clock to be output from the tmow pin. bit 0 cwos description 0 clock output from timer a is output (see tma) (initial value) 1 w is output section 9 timers rev. 6.00 aug 04, 2006 page 245 of 626 rej09b0144-0600 9.2.3 timer operation 1. interval timer operation when bit tma3 in timer mode register a (tma) is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt request register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested. * at overflow, tca returns to h'00 and starts counting up again. in this mode timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. note: * for details on interrupts, see section 3.3, interrupts. 2. real-time clock time base operation when bit tma3 in tma is set to 1, timer a functions as a real-time clock time base by counting clock signals output by prescaler w. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to their initial values of h'00. 3. clock output setting bit tmow in port mode register 1 (pmr1) to 1 causes a clock signal to be output at pin tmow. nine different clock output signals can be selected by means of bits tma7 to tma5 in tma and bit cwos in cwosr. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz or 38.4 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, watch mode, subactive mode, and subsleep mode. the 32.768 khz or 38.4 khz clock is output in all modes except the reset state. section 9 timers rev. 6.00 aug 04, 2006 page 246 of 626 rej09b0144-0600 9.2.4 timer a operation states table 9.4 summarizes the timer a operation states. table 9.4 timer a operation states operation mode reset active sleep watch sub- active sub- sleep standby module standby tca interval reset functions functions halted halted halted halted halted clock time base reset functions functions functions functions functions halted halted tma cwosr reset functions retained retained functions retained retained retained note: when the real-time clock time base function is selected as the internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/ (s) in the count cycle. 9.2.5 application note when bit 0 (tackstp) of the clock stop register 1 (ckstpr1) is cleared to 0, bit 3 (tma3) of the timer mode register a (tma) cannot be rewritten. set bit 0 (tackstp) of the clock stop register 1 (ckstpr1) to 1 before rewriting bit 3 (tma3) of the timer mode register a (tma). section 9 timers rev. 6.00 aug 04, 2006 page 247 of 626 rej09b0144-0600 9.3 timer c 9.3.1 overview timer c is an 8-bit timer that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer c are given below. ? choice of seven internal clock sources ( /8192, /2048, /512, /64, /16, /4, w/4) or an external clock (can be used to count external events). ? an interrupt is requested when the counter overflows. ? up/down-counter switching is possible by hardware or software. ? subactive mode and subsleep mode operation is possible when w/4 is selected as the internal clock, or when an external clock is selected. ? use of module standby mode enables this module to be placed in standby mode independently when not used. section 9 timers rev. 6.00 aug 04, 2006 page 248 of 626 rej09b0144-0600 2. block diagram figure 9.2 shows a block diagram of timer c. ud tmic w /4 pss tmc internal data bus tcc tlc irrtc legend: tmc: tcc: tlc: irrtc: pss: timer mode register c timer counter c timer load register c timer c overflow interrupt request flag prescaler s figure 9.2 block diagram of timer c 3. pin configuration table 9.5 shows the timer c pin configuration. table 9.5 pin configuration name abbr. i/o function timer c event input tmic input input pin for event input to tcc timer c up/down-count selection ud input timer c up/down select section 9 timers rev. 6.00 aug 04, 2006 page 249 of 626 rej09b0144-0600 4. register configuration table 9.6 shows the register configuration of timer c. table 9.6 timer c registers name abbr. r/w initial value address timer mode register c tmc r/w h'18 h'ffb4 timer counter c tcc r h'00 h'ffb5 timer load register c tlc w h'00 h'ffb5 clock stop register 1 ckstpr1 r/w h'ff h'fffa 9.3.2 register descriptions 1. timer mode register c (tmc) bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 4 ? 1 ? 3 ? 1 ? 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w tmc is an 8-bit read/write register for selecting the auto-reload function and input clock, and performing up/down-counter control. upon reset, tmc is initialized to h'18. bit 7: auto-reload function select (tmc7) bit 7 selects whether timer c is used as an interval timer or auto-reload timer. bit 7 tmc7 description 0 interval timer function selected (initial value) 1 auto-reload function selected section 9 timers rev. 6.00 aug 04, 2006 page 250 of 626 rej09b0144-0600 bits 6 and 5: counter up/down control (tmc6, tmc5) selects whether tcc up/down control is performed by hardware using ud pin input, or whether tcc functions as an up-counter or a down-counter. bit 6 tmc6 bit 5 tmc5 description 0 0 tcc is an up-counter (initial value) 0 1 tcc is a down-counter 1 * hardware control by ud pin input ud pin input high: down-counter ud pin input low: up-counter * : don?t care bits 4 and 3: reserved bits bits 4 and 3 are reserved; they are always read as 1 and cannot be modified. bits 2 to 0: clock select (tmc2 to tmc0) bits 2 to 0 select the clock input to tcc. for external event counting, either the rising or falling edge can be selected. bit 2 tmc2 bit 1 tmc1 bit 0 tmc0 description 000internal clock: /8192 (initial value) 001internal clock: /2048 010internal clock: /512 011internal clock: /64 100internal clock: /16 101internal clock: /4 110internal clock: w/4 111external event (tmic): rising or falling edge * note: * the edge of the external event signal is selected by bit ieg1 in the irq edge select register (iegr). see 1. irq edge select register (iegr) in 3.3.2 for details. irq1 must be set to 1 in port mode register 1 (pmr1) before setting 111 in bits tmc2 to tmc0. section 9 timers rev. 6.00 aug 04, 2006 page 251 of 626 rej09b0144-0600 2. timer counter c (tcc) bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r tcc is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. the clock source for input to this counter is selected by bits tmc2 to tmc0 in timer mode register c (tmc). tcc values can be read by the cpu at any time. when tcc overflows from h'ff to h'00 or to the value set in tlc, or underflows from h'00 to h'ff or to the value set in tlc, the irrtc bit in irr2 is set to 1. tcc is allocated to the same address as tlc. upon reset, tcc is initialized to h'00. 3. timer load register c (tlc) bit initial value read/write 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 4 tlc4 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w tlc is an 8-bit write-only register for setting the reload value of timer counter c (tcc). when a reload value is set in tlc, the same value is loaded into timer counter c as well, and tcc starts counting up from that value. when tcc overflows or underflows during operation in auto- reload mode, the tlc value is loaded into tcc. accordingly, overflow/underflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlc as to tcc. upon reset, tlc is initialized to h'00. section 9 timers rev. 6.00 aug 04, 2006 page 252 of 626 rej09b0144-0600 4. clock stop register 1 (ckstpr1) ? tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer c is described here. for details of the other bits, see the sections on the relevant modules. bit 1: timer c module standby mode control (tcckstp) bit 1 controls setting and clearing of module standby mode for timer c. tcckstp description 0 timer c is set to module standby mode 1 timer c module standby mode is cleared (initial value) 9.3.3 timer operation 1. interval timer operation when bit tmc7 in timer mode register c (tmc) is cleared to 0, timer c functions as an 8-bit interval timer. upon reset, tcc is initialized to h'00 and tmc to h'18, so tcc continues up-counting as an interval up-counter without halting immediately after a reset. the timer c operating clock is selected from seven internal clock signals output by prescalers s and w, or an external clock input at pin tmic. the selection is made by bits tmc2 to tmc0 in tmc. tcc up/down-count control can be performed either by software or hardware. the selection is made by bits tmc6 and tmc5 in tmc. after the count value in tcc reaches h'ff (h'00), the next clock input causes timer c to overflow (underflow), setting bit irrtc to 1 in irr2. if ientc = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested. at overflow (underflow), tcc returns to h'00 (h'ff) and starts counting up (down) again. section 9 timers rev. 6.00 aug 04, 2006 page 253 of 626 rej09b0144-0600 during interval timer operation (tmc7 = 0), when a value is set in timer load register c (tlc), the same value is set in tcc. note: for details on interrupts, see section 3.3, interrupts. 2. auto-reload timer operation setting bit tmc7 in tmc to 1 causes timer c to function as an 8-bit auto-reload timer. when a reload value is set in tlc, the same value is loaded into tcc, becoming the value from which tcc starts its count. after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow/underflow. the tlc value is then loaded into tcc, and the count continues from that value. the overflow/underflow period can be set within a range from 1 to 256 input clocks, depending on the tlc value. the clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmc7 = 1), when a new value is set in tlc, the tlc value is also set in tcc. 3. event counter operation timer c can operate as an event counter, counting rising or falling edges of an external event signal input at pin tmic. external event counting is selected by setting bits tmc2 to tmc0 in timer mode register c to all 1s (111). when timer c is used to count external event input, bit irq1 in pmr1 should be set to 1 and bit ien1 in ienr1 cleared to 0 to disable interrupt irq 1 requests. 4. tcc up/down control by hardware with timer c, tcc up/down control can be performed by ud pin input. when bit tmc6 is set to 1 in tmc, tcc functions as an up-counter when ud pin input is high, and as a down-counter when low. when using ud pin input, set bit ud to 1 in pmr3. section 9 timers rev. 6.00 aug 04, 2006 page 254 of 626 rej09b0144-0600 9.3.4 timer c operation states table 9.7 summarizes the timer c operation states. table 9.7 timer c operation states operation mode reset active sleep watch sub- active sub-sleep standby module standby tcc interval reset functions functions halted functions/ halted * functions/ halted * halted halted auto reload reset functions functions halted functions/ halted * functions/ halted * halted halted tmc reset functions retained retained functions retained retained retained note: * when w/4 is selected as the tcc internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when the counter is operated in subactive mode or subsleep mode, either select w/4 as the internal clock or select an external clock. the counter will not operate on any other internal clock. if w/4 is selected as the internal clock for the counter when w/8 has been selected as subclock sub , the lower 2 bits of the counter operate on the same cycle, and the operation of the least significant bit is unrelated to the operation of the counter. section 9 timers rev. 6.00 aug 04, 2006 page 255 of 626 rej09b0144-0600 9.3.5 usage note note the following regarding the operation of timer c. (1) counting errors caused by external event input timer counter errors may occur under the following conditions. conditions ? an external event (tmic) is used in subsleep mode. symptom ? the counter increments or decrements twice for a single external event input. approximate rate of occurrence the approximate rate of occurrence in cases where the external event input is not synchronized with internal operation is defined by the following equation. approximate rate of occurrence p = 30 ns / tsubcyc for example, if tsubcyc = 61.06 s (subclock w/2), p = 0.0005 (0.05%). if 2,000 external event inputs occur, there is a likelihood that one of them will cause the counter to increment or decrement twice (+2 or ?2). the symptom described is caused by the internal circuit configuration of the device and therefore difficult to avoid. therefore, it is not advisable to use the clock counter for applications requiring a high degree of accuracy. section 9 timers rev. 6.00 aug 04, 2006 page 256 of 626 rej09b0144-0600 9.4 timer f 9.4.1 overview timer f is a 16-bit timer with a built-in output compare function. as well as counting external events, timer f also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. timer f can also be used as two independent 8-bit timers (timer fh and timer fl). 1. features features of timer f are given below. ? choice of four internal clock sources ( /32, /16, /4, w/4) or an external clock (can be used as an external event counter) ? tmofh pin (tmofl pin) toggle output provided using a single compare match signal (toggle output initial value can be set) ? counter resetting by a compare match signal ? two interrupt sources: one compare match, one overflow ? can operate as two independent 8-bit timers (timer fh and timer fl) (in 8-bit mode). timer fh 8-bit timer * timer fl 8-bit timer/event counter internal clock choice of 4 ( /32, /16, /4, w/4) event input ? tmif pin toggle output one compare match signal, output to tmofh pin(initial value settable) one compare match signal, output to tmofl pin (initial value settable) counter reset counter can be reset by compare match signal interrupt sources one compare match one overflow note: * when timer f operates as a 16-bit timer, it operates on the timer fl overflow signal. ? operation in watch mode, subactive mode, and subsleep mode when w/4 is selected as the internal clock, timer f can operate in watch mode, subactive mode, and subsleep mode. ? use of module standby mode enables this module to be placed in standby mode independently when not used. section 9 timers rev. 6.00 aug 04, 2006 page 257 of 626 rej09b0144-0600 2. block diagram figure 9.3 shows a block diagram of timer f. pss toggle circuit toggle circuit tmif w /4 tmofl tmofh tcrf tcfl ocrfl tcfh ocrfh tcsrf comparator comparator match irrtfh irrtfl legend: tcrf: tcsrf: tcfh: tcfl: ocrfh: ocrfl: irrtfh: irrtfl: pss: timer control register f timer control/status register f 8-bit timer counter fh 8-bit timer counter fl output compare register fh output compare register fl timer fh interrupt request flag timer fl interrupt request flag prescaler s internal data bus figure 9.3 block diagram of timer f section 9 timers rev. 6.00 aug 04, 2006 page 258 of 626 rej09b0144-0600 3. pin configuration table 9.8 shows the timer f pin configuration. table 9.8 pin configuration name abbr. i/o function timer f event input tmif input event input pin for input to tcfl timer fh output tmofh output timer fh toggle output pin timer fl output tmofl output timer fl toggle output pin 4. register configuration table 9.9 shows the register configuration of timer f. table 9.9 timer f registers name abbr. r/w initial value address timer control register f tcrf w h'00 h'ffb6 timer control/status register f tcsrf r/w h'00 h'ffb7 8-bit timer counter fh tcfh r/w h'00 h'ffb8 8-bit timer counter fl tcfl r/w h'00 h'ffb9 output compare register fh ocrfh r/w h'ff h'ffba output compare register fl ocrfl r/w h'ff h'ffbb clock stop register 1 ckstpr1 r/w h'ff h'fffa section 9 timers rev. 6.00 aug 04, 2006 page 259 of 626 rej09b0144-0600 9.4.2 register descriptions 1. 16-bit timer counter (tcf) 8-bit timer counter (tcfh) 8-bit timer counter (tcfl) 15 14 13 12 11 10 9 8 tcf tcfh tcfl 76543210 0000000000000000 r/w bit initial value read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcf is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters tcfh and tcfl. in addition to the use of tcf as a 16-bit counter with tcfh as the upper 8 bits and tcfl as the lower 8 bits, tcfh and tcfl can also be used as independent 8-bit counters. tcfh and tcfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see section 9.4.3, cpu interface. tcfh and tcfl are each initialized to h'00 upon reset. a. 16-bit mode (tcf) when cksh2 is cleared to 0 in tcrf, tcf operates as a 16-bit counter. the tcf input clock is selected by bits cksl2 to cksl0 in tcrf. tcf can be cleared in the event of a compare match by means of cclrh in tcsrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf is 1 at this time, irrtfh is set to 1 in irr2, and if ientfh in ienr2 is 1, an interrupt request is sent to the cpu. b. 8-bit mode (tcfl/tcfh) when cksh2 is set to 1 in tcrf, tcfh and tcfl operate as two independent 8-bit counters. the tcfh (tcfl) input clock is selected by bits cksh2 to cksh0 (cksl2 to cksl0) in tcrf. tcfh (tcfl) can be cleared in the event of a compare match by means of cclrh (cclrl) in tcsrf. when tcfh (tcfl) overflows from h'ff to h'00, ovfh (ovfl) is set to 1 in tcsrf. if ovieh (oviel) in tcsrf is 1 at this time, irrtfh (irrtfl) is set to 1 in irr2, and if ientfh (ientfl) in ienr2 is 1, an interrupt request is sent to the cpu. section 9 timers rev. 6.00 aug 04, 2006 page 260 of 626 rej09b0144-0600 2. 16-bit output compare register (ocrf) 8-bit output compare register (ocrfh) 8-bit output compare register (ocrfl) 15 14 13 12 11 10 9 8 ocrf ocrfh ocrfl 76543210 1111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ocrf is a 16-bit read/write register composed of the two registers ocrfh and ocrfl. in addition to the use of ocrf as a 16-bit register with ocrfh as the upper 8 bits and ocrfl as the lower 8 bits, ocrfh and ocrfl can also be used as independent 8-bit registers. ocrfh and ocrfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see section 9.4.3, cpu interface. ocrfh and ocrfl are each initialized to h'ff upon reset. a. 16-bit mode (ocrf) when cksh2 is cleared to 0 in tcrf, ocrf operates as a 16-bit register. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. at the same time, irrtfh is set to 1 in irr2. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin by means of compare matches, and the output level can be set (high or low) by means of tolh in tcrf. b. 8-bit mode (ocrfh/ocrfl) when cksh2 is set to 1 in tcrf, ocrfh and ocrfl operate as two independent 8-bit registers. ocrfh contents are compared with tcfh, and ocrfl contents are with tcfl. when the ocrfh (ocrfl) and tcfh (tcfl) values match, cmfh (cmfl) is set to 1 in tcsrf. at the same time, irrtfh (irrtfl) is set to 1 in irr2. if ientfh (ientfl) in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin (tmofl pin) by means of compare matches, and the output level can be set (high or low) by means of tolh (toll) in tcrf. section 9 timers rev. 6.00 aug 04, 2006 page 261 of 626 rej09b0144-0600 3. timer control register f (tcrf) tolh cksl2 cksl1 cksl0 cksh2 cksh1 cksh0 toll 76543210 0 0000000 w www www w bit initial value read/write tcrf is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the tmofh and tmofl pins. tcrf is initialized to h'00 upon reset. bit 7: toggle output level h (tolh) bit 7 sets the tmofh pin output level. the output level is effective immediately after this bit is written. bit 7 tolh description 0 low level (initial value) 1 high level bits 6 to 4: clock select h (cksh2 to cksh0) bits 6 to 4 select the clock input to tcfh from among four internal clock sources or tcfl overflow. bit 6 cksh2 bit 5 cksh1 bit 4 cksh0 description 0 0 0 16-bit mode, counting on tcfl overflow signal (initial value) 001 010 011use prohibited 100internal clock: c ounting on /32 101internal clock: c ounting on /16 110internal clock: c ounting on /4 111internal clock: c ounting on w/4 section 9 timers rev. 6.00 aug 04, 2006 page 262 of 626 rej09b0144-0600 bit 3: toggle output level l (toll) bit 3 sets the tmofl pin output level. the output level is effective immediately after this bit is written. bit 3 toll description 0 low level (initial value) 1 high level bits 2 to 0: clock select l (cksl2 to cksl0) bits 2 to 0 select the clock input to tcfl from among four internal clock sources or external event input. bit 2 cksl2 bit 1 cksl1 bit 0 cksl0 description 000 001 counting on external event (tmif) rising/falling edge * (initial value) 010 011use prohibited 100internal clock: c ounting on /32 101internal clock: c ounting on /16 110internal clock: c ounting on /4 111internal clock: c ounting on w/4 note: * external event edge selection is set by ieg3 in the irq edge select register (iegr). for details, see 1. irq edge select register (iegr) in section 3.3.2. note that the timer f counter may increment if the setting of irq3 in port mode register 1 (pmr1) is changed from 0 to 1 while the tmif pin is low in order to change the tmif pin function. section 9 timers rev. 6.00 aug 04, 2006 page 263 of 626 rej09b0144-0600 4. timer control/status register f (tcsrf) ovfh cmfl oviel cclrl cmfh ovieh cclrh ovfl 76543210 0 0000000 r/w * r/w * r/w r/w r/w * r/w r/w r/w * note: * bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. bit initial value read/write tcsrf is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. tcsrf is initialized to h'00 upon reset. bit 7: timer overflow flag h (ovfh) bit 7 is a status flag indicating that tcfh has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 ovfh description 0 clearing condition: (initial value) after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting condition: set when tcfh overflows from h?ff to h?00 bit 6: compare match flag h (cmfh) bit 6 is a status flag indicating that tcfh has matched ocrfh. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6 cmfh description 0 clearing condition: (initial value) after reading cmfh = 1, cleared by writing 0 to cmfh 1 setting condition: set when the tcfh value matches the ocrfh value section 9 timers rev. 6.00 aug 04, 2006 page 264 of 626 rej09b0144-0600 bit 5: timer overflow interrupt enable h (ovieh) bit 5 selects enabling or disabling of interrupt generation when tcfh overflows. bit 5 ovieh description 0 tcfh overflow interrupt request is disabled (initial value) 1 tcfh overflow interrupt request is enabled bit 4: counter clear h (cclrh) in 16-bit mode, bit 4 selects whether tcf is cleared when tcf and ocrf match. in 8-bit mode, bit 4 selects whether tcfh is cleared when tcfh and ocrfh match. bit 4 cclrh description 0 16-bit mode: tcf clearing by compare match is disabled 8-bit mode: tcfh clearing by compare match is disabled (initial value) 1 16-bit mode: tcf clearing by compare match is enabled 8-bit mode: tcfh clearing by compare match is enabled bit 3: timer overflow flag l (ovfl) bit 3 is a status flag indicating that tcfl has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 3 ovfl description 0 clearing condition: (initial value) after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting condition: set when tcfl overflows from h?ff to h?00 section 9 timers rev. 6.00 aug 04, 2006 page 265 of 626 rej09b0144-0600 bit 2: compare match flag l (cmfl) bit 2 is a status flag indicating that tcfl has matched ocrfl. this flag is set by hardware and cleared by software. it cannot be set by software. bit 2 cmfl description 0 clearing condition: (initial value) after reading cmfl = 1, cleared by writing 0 to cmfl 1 setting condition: set when the tcfl value matches the ocrfl value bit 1: timer overflow interrupt enable l (oviel) bit 1 selects enabling or disabling of interrupt generation when tcfl overflows. bit 1 oviel description 0 tcfl overflow interrupt request is disabled (initial value) 1 tcfl overflow interrupt request is enabled bit 0: counter clear l (cclrl) bit 0 selects whether tcfl is cleared when tcfl and ocrfl match. bit 0 cclrl description 0 tcfl clearing by compare match is disabled (initial value) 1 tcfl clearing by compare match is enabled section 9 timers rev. 6.00 aug 04, 2006 page 266 of 626 rej09b0144-0600 5. clock stop register 1 (ckstpr1) ? tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer f is described here. for details of the other bits, see the sections on the relevant modules. bit 2: timer f module standby mode control (tfckstp) bit 2 controls setting and clearing of module standby mode for timer f. tfckstp description 0 timer f is set to module standby mode 1 timer f module standby mode is cleared (initial value) 9.4.3 cpu interface tcf and ocrf are 16-bit read/write registers, but the cpu is connected to the on-chip peripheral modules by an 8-bit data bus. when the cpu accesses these registers, it therefore uses an 8-bit temporary register (temp). in 16-bit mode, tcf read/write access and ocrf write access must be performed 16 bits at a time (using two consecutive byte-size mov instructions), and the upper byte must be accessed before the lower byte. data will not be transferred correctly if only the upper byte or only the lower byte is accessed. in 8-bit mode, there are no restrictions on the order of access. 1. write access write access to the upper byte results in transfer of the upper-byte write data to temp. next, write access to the lower byte results in transfer of the data in temp to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. section 9 timers rev. 6.00 aug 04, 2006 page 267 of 626 rej09b0144-0600 figure 9.4 shows an example in which h'aa55 is written to tcf. write to upper byte cpu (h'aa) temp (h'aa) tcfh ( ) tcfl ( ) bus interface module data bus write to lower byte cpu (h'55) temp (h'aa) tcfh (h'aa) tcfl (h'55) bus interface module data bus figure 9.4 write access to tcr (cpu tcf) section 9 timers rev. 6.00 aug 04, 2006 page 268 of 626 rej09b0144-0600 2. read access in access to tcf, when the upper byte is read the upper-byte data is transferred directly to the cpu and the lower-byte data is transferred to temp. next, when the lower byte is read, the lower-byte data in temp is transferred to the cpu. in access to ocrf, when the upper byte is read the upper-byte data is transferred directly to the cpu. when the lower byte is read, the lower-byte data is transferred directly to the cpu. figure 9.5 shows an example in which tcf is read when it contains h'aaff. read upper byte cpu (h'aa) temp (h'ff) tcfh (h'aa) tcfl (h'ff) bus interface module data bus read lower byte cpu (h'ff) temp (h'ff) tcfh (ab) * tcfl (00) * bus interface module data bus note: * h'ab00 if counter has been updated once. figure 9.5 read access to tcf (tcf cpu) section 9 timers rev. 6.00 aug 04, 2006 page 269 of 626 rej09b0144-0600 9.4.4 operation timer f is a 16-bit counter that increments on each input clock pulse. the timer f value is constantly compared with the value set in output compare register f, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. timer f can also function as two independent 8-bit timers. 1. timer f operation timer f has two operating modes, 16-bit timer mode and 8-bit timer mode. the operation in each of these modes is described below. a. operation in 16-bit timer mode when cksh2 is cleared to 0 in timer control register f (tcrf), timer f operates as a 16-bit timer. following a reset, timer counter f (tcf) is initialized to h'0000, output compare register f (ocrf) to h'ffff, and timer control register f (tcrf) and timer control/status register f (tcsrf) to h'00. the counter starts incrementing on external event (tmif) input. the external event edge selection is set by ieg3 in the irq edge select register (iegr). the timer f operating clock can be selected from four internal clocks or an external clock by means of bits cksl2 to cksl0 in tcrf. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu, and at the same time, tmofh pin output is toggled. if cclrh in tcsrf is 1, tcf is cleared. tmofh pin output can also be set by tolh in tcrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf and ientfh in ienr2 are both 1, an interrupt request is sent to the cpu. b. operation in 8-bit timer mode when cksh2 is set to 1 in tcrf, tcf operates as two independent 8-bit timers, tcfh and tcfl. the tcfh/tcfl input clock is selected by cksh2 to cksh0/cksl2 to cksl0 in tcrf. when the ocrfh/ocrfl and tcfh/tcfl values match, cmfh/cmfl is set to 1 in tcsrf. if ientfh/ientfl in ienr2 is 1, an interrupt request is sent to the cpu, and at the same time, tmofh pin/tmofl pin output is toggled. if cclrh/cclrl in tcsrf is 1, tcfh/tcfl is cleared. tmofh pin/tmofl pin output can also be set by tolh/toll in tcrf. when tcfh/tcfl overflows from h'ff to h'00, ovfh/ovfl is set to 1 in tcsrf. if ovieh/oviel in tcsrf and ientfh/ientfl in ienr2 are both 1, an interrupt request is sent to the cpu. section 9 timers rev. 6.00 aug 04, 2006 page 270 of 626 rej09b0144-0600 2. tcf increment timing tcf is incremented by clock input (internal clock or external event input). a. internal clock operation bits cksh2 to cksh0 or cksl2 to cksl0 in tcrf select one of four internal clock sources ( /32, /16, /4, or w/4) created by dividing the system clock ( or w). b. external event operation external event input is selected by clearing cksl2 to 0 in tcrf. tcf can increment on either the rising or falling edge of external event input. external event edge selection is set by ieg3 in the interrupt controller?s iegr register. an external event pulse width of at least 2 system clocks ( ) is necessary. shorter pulses will not be counted correctly. 3. tmofh/tmofl output timing in tmofh/tmofl output, the value set in tolh/toll in tcrf is output. the output is toggled by the occurrence of a compare match. figure 9.6 shows the output timing. tmif (when ieg3 = 1) count input clock tcf ocrf tmofh tmofl compare match signal nn n n n+1 n+1 figure 9.6 tmofh/tmofl output timing section 9 timers rev. 6.00 aug 04, 2006 page 271 of 626 rej09b0144-0600 4. tcf clear timing tcf can be cleared by a compare match with ocrf. 5. timer overflow flag (ovf) set timing ovf is set to 1 when tcf overflows from h'ffff to h'0000. 6. compare match flag set timing the compare match flag (cmfh or cmfl) is set to 1 when the tcf and ocrf values match. the compare match signal is generated in the last state during which the values match (when tcf is updated from the matching value to a new value). when tcf matches ocrf, the compare match signal is not generated until the next counter clock. 7. timer f operation modes timer f operation modes are shown in table 9.10. table 9.10 timer f operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby tcf reset functions functions functions/ halted * functions/ halted * functions/ halted * halted halted ocrf reset functions held held functions held held held tcrf reset functions held held functions held held held tcsrf reset functions held held functions held held held note: * when w /4 is selected as the tcf internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when the counter is operated in subactive mode, watch mode, or subsleep mode, w /4 must be selected as the internal clock. the counter will not operate if any other internal clock is selected. section 9 timers rev. 6.00 aug 04, 2006 page 272 of 626 rej09b0144-0600 9.4.5 application notes the following types of contention and operation can occur when timer f is used. 1. 16-bit timer mode in toggle output, tmofh pin output is toggled when all 16 bits match and a compare match signal is generated. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. tmofl pin output is unstable in 16-bit mode, and should not be used; the tmofl pin should be used as a port pin. if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. compare match flag cmfh is set when all 16 bits match and a compare match signal is generated. compare match flag cmfl is set if the setting conditions for the lower 8 bits are satisfied. when tcf overflows, ovfh is set. ovfl is set if the setting conditions are satisfied when the lower 8 bits overflow. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. 2. 8-bit timer mode a. tcfh, ocrfh in toggle output, tmofh pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. if an ocrfh write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfh clock. if a tcfh write and overflow signal output occur simultaneously, the overflow signal is not output. b. tcfl, ocrfl in toggle output, tmofl pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, toll data is output to the tmofl pin as a result of the tcrf write. section 9 timers rev. 6.00 aug 04, 2006 page 273 of 626 rej09b0144-0600 if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. 3. clear timer fh, timer fl interrupt request flags (irrtfh, irrtfl), timer overflow flags h, l (ovfh, ovfl) and compare match flags h, l (cmfh, cmfl) when w/4 is selected as the internal clock, ?interrupt factor generation signal? will be operated with w and the signal will be outputted with w width. and, ?overflow signal? and ?compare match signal? are controlled with 2 cycles of w signals. those signals are outputted with 2 cycles width of w (figure 9.7) in active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of ?interrupt factor generation signal?, same interrupt request flag is set. (figure 9.7 (1)) and, you cannot be cleared timer overflow flag and compare match flag during the term of validity of ?overflow signal? and ?compare match signal?. for interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer fh, timer fl interrupt might be repeated. (figure 9.7 (2)) therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. and, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register f (tcsrf) after the time that calculated with below (1) formula. for st of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of rte instruction when mulxu, divxu instruction is not used, 14 states when mulxu, divxu instruction is used) in subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear. the term of validity of ?interrupt factor generation signal? = 1 cycle of w + waiting time for completion of executing instruction + interrupt time synchronized with = 1/ w + st (1/ ) + (2/ ) (second).....(1) st: executing number of execution states section 9 timers rev. 6.00 aug 04, 2006 page 274 of 626 rej09b0144-0600 method 1 is recommended to operate for time efficiency. method 1 1. prohibit interrupt in interrupt handling routine (set ienfh, ienfl to 0). 2. after program process returned normal handling, clear interrupt request flags (irrtfh, irrtfl) after more than that calculated with (1) formula. 3. after read timer control status register f (tcsrf), clear timer overflow flags (ovfh, ovfl) and compare match flags (cmfh, cmfl). 4. operate interrupt permission (set ienfh, ienfl to 1). method 2 1. set interrupt handling routine time to more than time that calculated with (1) formula. 2. clear interrupt request flags (irrtfh, irrtfl) at the end of interrupt handling routine. 3. after read timer control status register f (tcsrf), clear timer overflow flags (ovfh, ovfl) and compare match flags (cmfh, cmfl). all above attentions are also applied in 16-bit mode and 8-bit mode. program process w interrupt request flag (irrtfh, irrtfl) interrupt factor generation signal (internal signal, nega-active) overflow signal, compare match signal (internal signal, nega-active) interrupt interrupt normal interrupt request flag clear interrupt request flag clear (1) (2) figure 9.7 clear interrupt request flag when interrupt factor generation signal is valid section 9 timers rev. 6.00 aug 04, 2006 page 275 of 626 rej09b0144-0600 4. timer counter (tcf) read/write when w/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on tcf is impossible. and, when read tcf, as the system clock and internal clock are mutually asynchronous, tcf synchronizes with synchronization circuit. this results in a maximum tcf read value error of 1. when read/write tcf in active (high-speed, medium-speed) mode is needed, please select internal clock except for w/4 before read/write. in subactive mode, even w/4 is selected as the internal clock, normal read/write tcf is possible. section 9 timers rev. 6.00 aug 04, 2006 page 276 of 626 rej09b0144-0600 9.5 timer g 9.5.1 overview timer g is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). high-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle. if input capture input is not set, timer g functions as an 8-bit interval timer. 1. features features of timer g are given below. ? choice of four internal clock sources ( /64, /32, /2, w/4) ? dedicated input capture functions for rising and falling edges ? level detection at counter overflow it is possible to detect whether overflow occurred when the input capture input signal was high or when it was low. ? selection of whether or not the counter value is to be cleared at the input capture input signal rising edge, falling edge, or both edges ? two interrupt sources: one input capture, one overflow. the input capture input signal rising or falling edge can be selected as the interrupt source. ? a built-in noise canceler eliminates high-frequency component noise in the input capture input signal. ? watch mode, subactive mode and subsleep mode operation is possible when w/4 is selected as the internal clock. ? use of module standby mode enables this module to be placed in standby mode independently when not used. section 9 timers rev. 6.00 aug 04, 2006 page 277 of 626 rej09b0144-0600 2. block diagram figure 9.8 shows a block diagram of timer g. pss tmg icrgf tcg icrgr noise canceler edge detector level detector irrtg w /4 tmig ncs legend: tmg: tcg: icrgf: icrgr: irrtg: ncs: pss: timer mode register g timer counter g input capture register gf input capture register gr timer g interrupt request flag noise canceler select prescaler s internal data bus figure 9.8 block diagram of timer g section 9 timers rev. 6.00 aug 04, 2006 page 278 of 626 rej09b0144-0600 3. pin configuration table 9.11 shows the timer g pin configuration. table 9.11 pin configuration name abbr. i/o function input capture input tmig input input capture input pin 4. register configuration table 9.12 shows the register configuration of timer g. table 9.12 timer g registers name abbr. r/w initial value address timer control register g tmg r/w h'00 h'ffbc timer counter g tcg ? h'00 ? input capture register gf icrgf r h'00 h'ffbd input capture register gr icrgr r h'00 h'ffbe clock stop register 1 ckstpr1 r/w h'ff h'fffa section 9 timers rev. 6.00 aug 04, 2006 page 279 of 626 rej09b0144-0600 9.5.2 register descriptions 1. timer counter (tcg) tcg7 tcg2 tcg1 tcg0 tcg6 tcg5 tcg4 tcg3 76543210 0 0000000 ? ??? ??? ? bit initial value read/write tcg is an 8-bit up-counter which is incremented by clock input. the input clock is selected by bits cks1 and cks0 in tmg. tmig in pmr1 is set to 1 to operate tcg as an input capture timer, or cleared to 0 to operate tcg as an interval timer * . in input capture timer operation, the tcg value can be cleared by the rising edge, falling edge, or both edges of the input capture input signal, according to the setting made in tmg. when tcg overflows from h'ff to h'00, if ovie in tmg is 1, irrtg is set to 1 in irr2, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see section 3.3, interrupts. tcg cannot be read or written by the cpu. it is initialized to h'00 upon reset. note: * an input capture signal may be generated when tmig is modified. section 9 timers rev. 6.00 aug 04, 2006 page 280 of 626 rej09b0144-0600 2. input capture register gf (icrgf) icrgf7 icrgf2 icrgf1 icrgf0 icrgf6 icrgf5 icrgf4 icrgf3 76543210 0 0000000 r rrr rrr r bit initial value read/write icrgf is an 8-bit read-only register. when a falling edge of the input capture input signal is detected, the current tcg value is transferred to icrgf. if iiegs in tmg is 1 at this time, irrtg is set to 1 in irr2, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see section 3.3, interrupts. to ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2 or 2 sub (when the noise canceler is not used). icrgf is initialized to h'00 upon reset. 3. input capture register gr (icrgr) icrgr7 icrgr2 icrgr1 icrgr0 icrgr6 icrgr5 icrgr4 icrgr3 76543210 0 0000000 r rrr rrr r bit initial value read/write icrgr is an 8-bit read-only register. when a rising edge of the input capture input signal is detected, the current tcg value is transferred to icrgr. if iiegs in tmg is 1 at this time, irrtg is set to 1 in irr2, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see section 3.3, interrupts. to ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2 or 2 sub (when the noise canceler is not used). icrgr is initialized to h'00 upon reset. section 9 timers rev. 6.00 aug 04, 2006 page 281 of 626 rej09b0144-0600 4. timer mode register g (tmg) ovfh cclr0 cks1 cks0 ovfl ovie iiegs cclr1 76543210 0 0000000 r/w * r/w r/w r/w r/w * r/w r/w r/w bit: initial value: read/write: note: * bits 7 and 6 can only be written with 0, for flag clearing. tmg is an 8-bit read/write register that performs tcg clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags. tmg is initialized to h'00 upon reset. bit 7: timer overflow flag h (ovfh) bit 7 is a status flag indicating that tcg has overflowed from h'ff to h'00 when the input capture input signal is high. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 ovfh description 0 clearing condition: (initial value) after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting condition: set when tcg overflows from h'ff to h'00 bit 6: timer overflow flag l (ovfl) bit 6 is a status flag indicating that tcg has overflowed from h'ff to h'00 when the input capture input signal is low, or in interval operation. this flag is set by hardware and cleared by software. it cannot be set by software. section 9 timers rev. 6.00 aug 04, 2006 page 282 of 626 rej09b0144-0600 bit 6 ovfl description 0 clearing condition: (initial value) after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting condition: set when tcg overflows from h'ff to h'00 bit 5: timer overflow interrupt enable (ovie) bit 5 selects enabling or disabling of interrupt generation when tcg overflows. bit 5 ovie description 0 tcg overflow interrupt request is disabled (initial value) 1 tcg overflow interrupt request is enabled bit 4: input capture interrupt edge select (iiegs) bit 4 selects the input capture input signal edge that generates an interrupt request. bit 4 iiegs description 0 interrupt generated on rising edge of input capture input signal (initial value) 1 interrupt generated on falling edge of input capture input signal bits 3 and 2: counter clear 1 and 0 (cclr1, cclr0) bits 3 and 2 specify whether or not tcg is cleared by the rising edge, falling edge, or both edges of the input capture input signal. bit 3 cclr1 bit 2 cclr0 description 0 0 tcg clearing is disabled (initial value) 0 1 tcg cleared by falling edge of input capture input signal 1 0 tcg cleared by rising edge of input capture input signal 1 1 tcg cleared by both edges of input capture input signal section 9 timers rev. 6.00 aug 04, 2006 page 283 of 626 rej09b0144-0600 bits 1 and 0: clock select (cks1, cks0) bits 1 and 0 select the clock input to tcg from among four internal clock sources. bit 1 cks1 bit 0 cks0 description 0 0 internal clock: counting on /64 (initial value) 0 1 internal clock: counting on /32 1 0 internal clock: counting on /2 1 1 internal clock: counting on w/4 5. clock stop register 1 (ckstpr1) ? tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer g is described here. for details of the other bits, see the sections on the relevant modules. bit 3: timer g module standby mode control (tgckstp) bit 3 controls setting and clearing of module standby mode for timer g. tgckstp description 0 timer g is set to module standby mode 1 timer g module standby mode is cleared (initial value) section 9 timers rev. 6.00 aug 04, 2006 page 284 of 626 rej09b0144-0600 9.5.3 noise canceler the noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. the noise canceler is set by ncs * in pmr3. figure 9.9 shows a block diagram of the noise canceler. c dq latch c dq latch c dq latch c dq latch c dq latch match detector noise canceler output sampling clock input capture input signal sampling clock t ? t: set by cks1 and cks0 figure 9.9 noise canceler block diagram the noise canceler consists of five latch circuits connected in series and a match detector circuit. when the noise cancellation function is not used (ncs = 0), the system clock is selected as the sampling clock. when the noise cancellation function is used (ncs = 1), the sampling clock is the internal clock selected by cks1 and cks0 in tmg, the input capture input is sampled on the rising edge of this clock, and the data is judged to be correct when all the latch outputs match. if all the outputs do not match, the previous value is retained. after a reset, the noise canceler output is initialized when the falling edge of the input capture input signal has been sampled five times. therefore, after making a setting for use of the noise cancellation function, a pulse with at least five times the width of the sampling clock is a dependable input capture signal. even if noise cancellation is not used, an input capture input signal pulse width of at least 2 or 2 sub is necessary to ensure that input capture operations are performed properly note: * an input capture signal may be generated when the ncs bit is modified. section 9 timers rev. 6.00 aug 04, 2006 page 285 of 626 rej09b0144-0600 figure 9.10 shows an example of noise canceler timing. in this example, high-level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise. input capture input signal sampling clock noise canceler output eliminated as noise figure 9.10 noise canceler timing (example) section 9 timers rev. 6.00 aug 04, 2006 page 286 of 626 rej09b0144-0600 9.5.4 operation timer g is an 8-bit timer with built-in input capture and interval functions. 1. timer g functions timer g is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. the operation of these two functions is described below. a. input capture timer operation when the tmig bit is set to 1 in port mode register 1 (pmr1), timer g functions as an input capture timer * . in a reset, timer mode register g (tmg), timer counter g (tcg), input capture register gf (icrgf), and input capture register gr (icrgr) are all initialized to h?00. following a reset, tcg starts incrementing on the /64 internal clock. the input clock can be selected from four internal clock sources by bits cks1 and cks0 in tmg. when a rising edge/falling edge is detected in the input capture signal input from the tmig pin, the tcg value at that time is transferred to icrgr/icrgf. when the edge selected by iiegs in tmg is input, irrtg is set to 1 in irr2, and if the ientg bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. for details of the interrupt, see section 3.3, interrupts. tcg can be cleared by a rising edge, falling edge, or both edges of the input capture signal, according to the setting of bits cclr1 and cclr0 in tmg. if tcg overflows when the input capture signal is high, the ovfh bit is set in tmg; if tcg overflows when the input capture signal is low, the ovfl bit is set in tmg. if the ovie bit in tmg is 1 when these bits are set, irrtg is set to 1 in irr2, and if the ientg bit in ienr2 is 1, timer g sends an interrupt request to the cpu. for details of the interrupt, see section 3.3, interrupts. timer g has a built-in noise canceler that enables high-frequency component noise to be eliminated from pulses input from the tmig pin. for details, see section 9.5.3, noise canceler. note: * an input capture signal may be generated when tmig is modified. section 9 timers rev. 6.00 aug 04, 2006 page 287 of 626 rej09b0144-0600 b. interval timer operation when the tmig bit is cleared to 0 in pmr1, timer g functions as an interval timer. following a reset, tcg starts incrementing on the /64 internal clock. the input clock can be selected from four internal clock sources by bits cks1 and cks0 in tmg. tcg increments on the selected clock, and when it overflows from h?ff to h?00, the ovfl bit is set to 1 in tmg. if the ovie bit in tmg is 1 at this time, irrtg is set to 1 in irr2, and if the ientg bit in ienr2 is 1, timer g sends an interrupt request to the cpu. for details of the interrupt, see section 3.3, interrupts. 2. increment timing tcg is incremented by internal clock input. bits cks1 and cks0 in tmg select one of four internal clock sources ( /64, /32, /2, or w/4) created by dividing the system clock ( ) or watch clock ( w). 3. input capture input timing a. without noise cancellation function for input capture input, dedicated input capture functions are provided for rising and falling edges. figure 9.11 shows the timing for rising/falling edge input capture input. input capture input signal input capture signal f input capture signal r figure 9.11 input capture input timing (without noise cancellation function) b. with noise cancellation function when noise cancellation is performed on the input capture input, the passage of the input capture signal through the noise canceler results in a delay of five sampling clock cycles from the input capture input signal edge. figure 9.12 shows the timing in this case. section 9 timers rev. 6.00 aug 04, 2006 page 288 of 626 rej09b0144-0600 input capture input signal sampling clock noise canceler output input capture signal r figure 9.12 input capture input timing (with noise cancellation function) 4. timing of input capture by input capture input figure 9.13 shows the timing of input capture by input capture input input capture signal tcg n-1 n n h'xx n+1 input capture register figure 9.13 timing of input capture by input capture input section 9 timers rev. 6.00 aug 04, 2006 page 289 of 626 rej09b0144-0600 5. tgc clear timing tcg can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. figure 9.14 shows the timing for clearing by both edges. input capture input signal input capture signal f input capture signal r tcg n n h'00 h'00 figure 9.14 tcg clear timing section 9 timers rev. 6.00 aug 04, 2006 page 290 of 626 rej09b0144-0600 6. timer g operation modes timer g operation modes are shown in table 9.13. table 9.13 timer g operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby tcg input capture reset functions * functions * functions/ halted * functions/ halted * functions/ halted * halted halted interval reset functions * functions * functions/ halted * functions/ halted * functions/ halted * halted halted icrgf reset functions * functions * functions/ halted * functions/ halted * functions/ halted * held held icrgr reset functions * functions * functions halted * functions/ halted * functions/ halted * held held tmg reset functions held held functions held held held note: * when w/4 is selected as the tcg internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when w/4 is selected as the tcg internal clock in watch mode, tcg and the noise canceler operate on the w/4 internal clock without regard to the sub subclock ( w/8, w/4, w/2). note that when another internal clock is selected, tcg and the noise canceler do not operate, and input of the input capture input signal does not result in input capture. to be operated timer g in subactive mode or subsleep mode, select w/4 for internal clock of tcg and also select w/2 for sub clock sub . when another internal clock is selected and when another sub clock ( w/8, w/4) is selected, tcg and noise canceler do not operate. section 9 timers rev. 6.00 aug 04, 2006 page 291 of 626 rej09b0144-0600 9.5.5 application notes 1. internal clock switching and tcg operation depending on the timing, tcg may be incremented by a switch between difference internal clock sources. table 9.14 shows the relation between internal clock switchover timing (by write to bits cks1 and cks0) and tcg operation. when tcg is internally clocked, an increment pulse is generated on detection of the falling edge of an internal clock signal, which is divided from the system clock ( ) or subclock ( w). for this reason, in a case like no. 3 in table 9.14 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing tcg to increment. table 9.14 internal clock switching and tcg operation no. clock levels before and after modifying bits cks1 and cks0 tcg operation 1 goes from low level to low level clock before switching clock after switching count clock tcg n n+1 write to cks1 and cks0 2 goes from low level to high level clock before switching clock before switching count clock tcg n n+1 n+2 write to cks1 and cks0 section 9 timers rev. 6.00 aug 04, 2006 page 292 of 626 rej09b0144-0600 no. clock levels before and after modifying bits cks1 and cks0 tcg operation 3 goes from high level to low level * tcg n n+1 n+2 clock before switching clock before switching count clock write to cks1 and cks0 4 goes from high level to high level tcg n n+1 n+2 clock before switching clock before switching count clock write to cks1 and cks0 note: * the switchover is seen as a falling edge, and tcg is incremented. section 9 timers rev. 6.00 aug 04, 2006 page 293 of 626 rej09b0144-0600 2. notes on port mode register modification the following points should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceler function. ? switching input capture input pin function note that when the pin function is switched by modifying tmig in port mode register 1 (pmr1), which performs input capture input pin control, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9.15. table 9.15 input capture input signal input edges due to input capture input pin switching, and conditions for their occurrence input capture input signal input edge conditions generation of rising edge when tmig is modified from 0 to 1 while the tmig pin is high when ncs is modified from 0 to 1 while the tmig pin is high, then tmig is modified from 0 to 1 before the signal is sampled five times by the noise canceler generation of falling edge when tmig is modified from 1 to 0 while the tmig pin is high when ncs is modified from 0 to 1 while the tmig pin is low, then tmig is modified from 0 to 1 before the signal is sampled five times by the noise canceler when ncs is modified from 0 to 1 while the tmig pin is high, then tmig is modified from 1 to 0 after the signal is sampled five times by the noise canceler note: when the p1 3 pin is not set as an input capture input pin, the timer g input capture input signal is low. section 9 timers rev. 6.00 aug 04, 2006 page 294 of 626 rej09b0144-0600 ? switching input capture input noise canceler function when performing noise canceler function switching by modifying ncs in port mode register 3 (pmr3), which controls the input capture input noise canceler, tmig should first be cleared to 0. note that if ncs is modified without first clearing tmig, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9.16. table 9.16 input capture input signal input edges due to noise canceler function switching, and conditions for their occurrence input capture input signal input edge conditions generation of rising edge when the tmig pin level is switched from low to high while tmig is set to 1, then ncs is modified from 0 to 1 before the signal is sampled five times by the noise canceler generation of falling edge when the tmig pin level is switched from high to low while tmig is set to 1, then ncs is modified from 1 to 0 before the signal is sampled five times by the noise canceler when the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (iiegs) bit, the interrupt request flag will be set to 1. the interrupt request flag should therefore be cleared to 0 before use. figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag clearing. when switching the pin function, set the interrupt-disabled state before manipulating the port mode register, then, after the port mode register operation has been performed, wait for the time required to confirm the input capture input signal as an input capture signal (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), before clearing the interrupt enable flag to 0. there are two ways of preventing interrupt request flag setting when the pin function is switched: by controlling the pin level so that the conditions shown in tables 9.15 and 9.16 are not satisfied, or by setting the opposite of the generated edge in the iiegs bit in tmg. section 9 timers rev. 6.00 aug 04, 2006 page 295 of 626 rej09b0144-0600 set i bit to 1 in ccr manipulate port mode register tmig confirmation time clear interrupt request flag to 0 clear i bit to 0 in ccr disable interrupts. (interrupts can also be disabled by manipulating the interrupt enable bit in interrupt enable register 2.) after manipulating he port mode register, wait for the tmig confirmation time (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), then clear the interrupt enable flag to 0. enable interrupts figure 9.15 port mode register manipulation and interrupt enable flag clearing procedure 9.5.6 timer g application example using timer g, it is possible to measure the high and low widths of the input capture input signal as absolute values. for this purpose, cclr1 and cclr0 should both be set to 1 in tmg. figure 9.16 shows an example of the operation in this case. counter cleared tcg h'ff h'00 input capture input signal input capture register gf input capture register gr figure 9.16 timer g application example section 9 timers rev. 6.00 aug 04, 2006 page 296 of 626 rej09b0144-0600 9.6 watchdog timer 9.6.1 overview the watchdog timer has an 8-bit counter that is incremented by an input clock. if a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1. features features of the watchdog timer are given below. ? incremented by internal clock source ( /8192 or w/32). ? a reset signal is generated when the counter overflows. the overflow period can be set from from 1 to 256 times 8192/ or 32/ w (from approximately 4 ms to 1000 ms when = 2.00 mhz). ? use of module standby mode enables this module to be placed in standby mode independently when not used. 2. block diagram figure 9.17 shows a block diagram of the watchdog timer. pss tcsrw tcw /8192 notation: tcsrw: tcw: pss: w /32 internal data bus reset signal timer control/status register w timer counter w prescaler s figure 9.17 block diagram of watchdog timer section 9 timers rev. 6.00 aug 04, 2006 page 297 of 626 rej09b0144-0600 3. register configuration table 9.17 shows the register configuration of the watchdog timer. table 9.17 watchdog timer registers name abbr. r/w initial value address timer control/status register w tcsrw r/w h'aa h'ffb2 timer counter w tcw r/w h'00 h'ffb3 clock stop register 2 ckstp2 r/w h'ff h'fffb port mode register 3 pmr3 r/w h'00 h'ffca 9.6.2 register descriptions 1. timer control/status register w (tcsrw) bit initial value read/write 7 b6wi 1 r 6 tcwe 0 r/(w) * 5 b4wi 1 r 4 tcsrwe 0 r/(w) * 3 b2wi 1 r 0 wrst 0 r/(w) * 2 wdon 0 r/(w) * 1 b0wi 1 r note: * write is permitted only under certain conditions, which are given in the descriptions of the individual bits. tcsrw is an 8-bit read/write register that controls write access to tcw and tcsrw itself, controls watchdog timer operations, and indicates operating status. bit 7: bit 6 write inhibit (b6wi) bit 7 controls the writing of data to bit 6 in tcsrw. bit 7 b6wi description 0 bit 6 is write-enabled 1 bit 6 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. section 9 timers rev. 6.00 aug 04, 2006 page 298 of 626 rej09b0144-0600 bit 6: timer counter w write enable (tcwe) bit 6 controls the writing of data to tcw. bit 6 tcwe description 0 data cannot be written to tcw (initial value) 1 data can be written to tcw bit 5: bit 4 write inhibit (b4wi) bit 5 controls the writing of data to bit 4 in tcsrw. bit 5 b4wi description 0 bit 4 is write-enabled 1 bit 4 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. bit 4: timer control/status register w write enable (tcsrwe) bit 4 controls the writing of data to tcsrw bits 2 and 0. bit 4 tcsrwe description 0 data cannot be written to bits 2 and 0 (initial value) 1 data can be written to bits 2 and 0 bit 3: bit 2 write inhibit (b2wi) bit 3 controls the writing of data to bit 2 in tcsrw. bit 3 b2wi description 0 bit 2 is write-enabled 1 bit 2 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. section 9 timers rev. 6.00 aug 04, 2006 page 299 of 626 rej09b0144-0600 bit 2: watchdog timer on (wdon) bit 2 enables watchdog timer operation. bit 2 wdon description 0 watchdog timer operation is disabled (initial value) clearing condition: reset, or when tcsrwe = 1 and 0 is written in both b2wi and wdon 1 watchdog timer operation is enabled setting condition: when tcsrwe = 1 and 0 is written in b2wi and 1 is written in wdon counting starts when this bit is set to 1, and stops when this bit is cleared to 0. bit 1: bit 0 write inhibit (b0wi) bit 1 controls the writing of data to bit 0 in tcsrw. bit 1 b0wi description 0 bit 0 is write-enabled 1 bit 0 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. bit 0: watchdog timer reset (wrst) bit 0 indicates that tcw has overflowed, generating an internal reset signal. the internal reset signal generated by the overflow resets the entire chip. wrst is cleared to 0 by a reset from the res pin, or when software writes 0. bit 0 wrst description 0 clearing condition: reset by res pin when tcsrwe = 1, and 0 is written in both b0wi and wrst 1 setting condition: when tcw overflows and an internal reset signal is generated section 9 timers rev. 6.00 aug 04, 2006 page 300 of 626 rej09b0144-0600 2. timer counter w (tcw) bit initial value read/write 7 tcw7 0 r/w 6 tcw6 0 r/w 5 tcw5 0 r/w 4 tcw4 0 r/w 3 tcw3 0 r/w 0 tcw0 0 r/w 2 tcw2 0 r/w 1 tcw1 0 r/w tcw is an 8-bit read/write up-counter, which is incremented by internal clock input. the input clock is /8192 or w/32. the tcw value can always be written or read by the cpu. when tcw overflows from h'ff to h'00, an internal reset signal is generated and wrst is set to 1 in tcsrw. upon reset, tcw is initialized to h'00. 3. clock stop register 2 (ckstpr2) ? wdckstp pwckstp ldckstp ??? aeckstp 76543210 1 1111111 ? r/w r/w r/w ??? r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the watchdog timer is described here. for details of the other bits, see the sections on the relevant modules. bit 2: watchdog timer module standby mode control (wdckstp) bit 2 controls setting and clearing of module standby mode for the watchdog timer. wdckstp description 0 watchdog timer is set to module standby mode 1 watchdog timer module standby mode is cleared (initial value) note: wdckstp is valid when the wdon bit is cleared to 0 in timer control/status register w (tcsrw). if wdckstp is set to 0 while wdon is set to 1 (during watchdog timer operation), 0 will be set in wdckstp but the watchdog timer will continue its watchdog function and will not enter module standby mode. when the watchdog function ends and wdon is cleared to 0 by software, the wdckstp setting will become valid and the watchdog timer will enter module standby mode. section 9 timers rev. 6.00 aug 04, 2006 page 301 of 626 rej09b0144-0600 4. port mode register 3 (pmr3) bit 76543210 aevl aevh wdcks ncs irq0 reso ud pwm initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pmr3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3 pins. only the bit relating to the watchdog timer is described here. for details of the other bits, see section 8, i/o ports. bit 5: watchdog timer source clock select (wdcks) wdcks description 0 /8192 selected (initial value) 1 w/32 selected 9.6.3 timer operation the watchdog timer has an 8-bit counter (tcw) that is incremented by clock input ( /8192 or w/32). the input clock is selected by bit wdcks in port mode register 3 (pmr3): /8192 is selected when wdcks is cleared to 0, and w/32 when set to 1. when tcsrwe = 1 in tcsrw, if 0 is written in b2wi and 1 is simultaneously written in wdon, tcw starts counting up. when the tcw count reaches h'ff, the next clock input causes the watchdog timer to overflow, and an internal reset signal is generated one reference clock ( or sub ) cycle later. the internal reset signal is output for 512 clock cycles of the osc clock. it is possible to write to tcw, causing tcw to count up from the written value. the overflow period can be set in the range from 1 to 256 input clocks, depending on the value written in tcw. figure 9.18 shows an example of watchdog timer operations. section 9 timers rev. 6.00 aug 04, 2006 page 302 of 626 rej09b0144-0600 h'f8 tcw overflow start h'f8 written in tcw h'f8 written in tcw reset internal reset signal 512 osc clock cycles h'ff h'00 tcw count value example: = 2 mhz and the desired overflow period is 30 ms. 2 10 6 8192 the value set in tcw should therefore be 256 ? 8 = 248 (h'f8). 30 10 ? 3 = 7.3 figure 9.18 typical watchdog timer operations (example) 9.6.4 watchdog timer operation states table 9.18 summarizes the watchdog timer operation states. table 9.18 watchdog timer operation states operation mode reset active sleep watch sub- active sub- sleep standby module standby tcw reset functions functions halted functions/ halted * halted halted halted tcsrw reset functions functions retained functions/ halted * retained retained retained note: * functions when w/32 is selected as the input clock. section 9 timers rev. 6.00 aug 04, 2006 page 303 of 626 rej09b0144-0600 9.7 asynchronous event counter (aec) 9.7.1 overview the asynchronous event counter is incremented by external event clock input. 1. features features of the asynchronous event counter are given below. ? can count asynchronous events can count external events input asynchronously without regard to the operation of base clocks and sub . the counter has a 16-bit configuration, enabling it to count up to 65536 (2 16 ) events. ? can also be used as two independent 8-bit event counter channels. ? counter resetting and halting of the count-up function controllable by software ? automatic interrupt generation on detection of event counter overflow ? use of module standby mode enables this module to be placed in standby mode independently when not used. section 9 timers rev. 6.00 aug 04, 2006 page 304 of 626 rej09b0144-0600 2. block diagram figure 9.19 shows a block diagram of the asynchronous event counter. eccsr ech ecl irrec internal data bus ovl ovh ck ck aevl aevh event counter control/status register event counter h event counter l asynchronous event input h asynchronous event input l event counter overflow interrupt request flag legend: eccsr: ech: ecl: aevh: aevl: irrec: figure 9.19 block diagram of asynchronous event counter 3. pin configuration table 9.19 shows the asynchronous event counter pin configuration. table 9.19 pin configuration name abbr. i/o function asynchronous event input h aevh input event input pin for input to event counter h asynchronous event input l aevl input event input pin for input to event counter l section 9 timers rev. 6.00 aug 04, 2006 page 305 of 626 rej09b0144-0600 4. register configuration table 9.20 shows the register configuration of the asynchronous event counter. table 9.20 asynchronous event counter registers name abbr. r/w initial value address event counter control/status register eccsr r/w h'00 h'ff95 event counter h ech r h'00 h'ff96 event counter l ecl r h'00 h'ff97 clock stop register 2 ckstp2 r/w h'ff h'fffb 9.7.2 register descriptions 1. event counter control/status register (eccsr) ovh cuel crch crcl ovl ? ch2 cueh 76543210 0 0000000 r/w * r/w r/w r/w r/w * r/w r/w r/w bit note: * bits 7 and 6 can only be written with 0, for flag clearing. initial value read/write eccsr is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function. eccsr is initialized to h'00 upon reset. section 9 timers rev. 6.00 aug 04, 2006 page 306 of 626 rej09b0144-0600 bit 7: counter overflow flag h (ovh) bit 7 is a status flag indicating that ech has overflowed from h'ff to h'00. this flag is set when ech overflows. it is cleared by software but cannot be set by software. ovh is cleared by reading it when set to 1, then writing 0. when ech and ecl are used as a 16-bit event counter with ch2 cleared to 0, ovh functions as a status flag indicating that the 16-bit event counter has overflowed from h'ffff to h'0000. bit 7 ovh description 0 ech has not overflowed (initial value) clearing condition: after reading ovh = 1, cleared by writing 0 to ovh 1 ech has overflowed setting condition: set when ech overflows from h?ff to h?00 bit 6: counter overflow flag l (ovl) bit 6 is a status flag indicating that ecl has overflowed from h'ff to h'00. this flag is set when ecl overflows. it is cleared by software but cannot be set by software. ovl is cleared by reading it when set to 1, then writing 0. bit 6 ovl description 0 ecl has not overflowed (initial value) clearing condition: after reading ovl = 1, cleared by writing 0 to ovl 1 ecl has overflowed setting condition: set when ecl overflows from h'ff to h'00 while ch2 is set to 1 bit 5: reserved bit bit 5 is reserved; it can be read and written, and is initialized to 0 upon reset. section 9 timers rev. 6.00 aug 04, 2006 page 307 of 626 rej09b0144-0600 bit 4: channel select (ch2) bit 4 selects whether ech and ecl are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels. when ch2 is cleared to 0, ech and ecl function as a 16-bit event counter which is incremented each time an event clock is input to the aevl pin as asynchronous event input. in this case, the overflow signal from ecl is selected as the ech input clock. when ch2 is set to 1, ech and ecl function as independent 8-bit event counters which are incremented each time an event clock is input to the aevh or aevl pin, respectively, as asynchronous event input. bit 4 ch2 description 0 ech and ecl are used together as a single-channel 16-bit event counter (initial value) 1 ech and ecl are used as two independent 8-bit event counter channels bit 3: count-up enable h (cueh) bit 3 enables event clock input to ech. when 1 is written to this bit, event clock input is enabled and increments the counter. when 0 is written to this bit, event clock input is disabled and the ech value is held. the aevh pin or the ecl overflow signal can be selected as the event clock source by bit ch2. bit 3 cueh description 0 ech event clock input is disabled (initial value) ech value is held 1 ech event clock input is enabled bit 2: count-up enable l (cuel) bit 3 enables event clock input to ecl. when 1 is written to this bit, event clock input is enabled and increments the counter. when 0 is written to this bit, event clock input is disabled and the ecl value is held. bit 2 cuel description 0 ecl event clock input is disabled (initial value) ecl value is held 1 ecl event clock input is enabled section 9 timers rev. 6.00 aug 04, 2006 page 308 of 626 rej09b0144-0600 bit 1: counter reset control h (crch) bit 1 controls resetting of ech. when this bit is cleared to 0, ech is reset. when 1 is written to this bit, the counter reset is cleared and the ech count-up function is enabled. bit 1 crch description 0 ech is reset (initial value) 1 ech reset is cleared and count-up function is enabled bit 0: counter reset control l (crcl) bit 0 controls resetting of ecl. when this bit is cleared to 0, ecl is reset. when 1 is written to this bit, the counter reset is cleared and the ecl count-up function is enabled. bit 0 crcl description 0 ecl is reset (initial value) 1 ecl reset is cleared and count-up function is enabled 2. event counter h (ech) ech7 ech2 ech1 ech0 ech6 ech5 ech4 ech3 76543210 0 0000000 r rrr rrr r bit initial value read/write ech is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ecl. either the external asynchronous event aevh pin or the overflow signal from lower 8-bit counter ecl can be selected as the input clock source by bit ch2. ech can be cleared to h'00 by software, and is also initialized to h'00 upon reset. section 9 timers rev. 6.00 aug 04, 2006 page 309 of 626 rej09b0144-0600 3. event counter l (ecl) ecl is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ech. the event clock from the external asynchronous event aevl pin is used as the input clock source. ecl can be cleared to h'00 by software, and is also initialized to h'00 upon reset. ecl7 ecl2 ecl1 ecl0 ecl6 ecl5 ecl4 ecl3 76543210 0 0000000 r rrr rrr r bit initial value read/write 4. clock stop register 2 (ckstpr2) ? wdckstp pwckstp ldckstp ??? aeckstp 76543210 1 1111111 ? r/w r/w r/w ??? r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the asynchronous event counter is described here. for details of the other bits, see the sections on the relevant modules. bit 3: asynchronous event counter module standby mode control (aeckstp) bit 3 controls setting and clearing of module standby mode for the asynchronous event counter. aeckstp description 0 asynchronous event counter is set to module standby mode 1 asynchronous event counter module standby mode is cleared (initial value) section 9 timers rev. 6.00 aug 04, 2006 page 310 of 626 rej09b0144-0600 9.7.3 operation 1. 16-bit event counter operation when bit ch2 is cleared to 0 in eccsr, ech and ecl operate as a 16-bit event counter. figure 9.20 shows an example of the software processing when ech and ecl are used as a 16-bit event counter. start end clear ch2 to 0 clear cueh, cuel, crch, and crcl to 0 clear ovh and ovl to 0 set cueh, cuel, crch, and crcl to 1 figure 9.20 example of software processing when using ech and ecl as 16-bit event counter as ch2 is cleared to 0 by a reset, ech and ecl operate as a 16-bit event counter after a reset. they can also be used as a 16-bit event counter by carrying out the software processing shown in the example in figure 9.20. the operating clock source is asynchronous event input from the aevl pin. when the next clock is input after the count value reaches h'ff in both ech and ecl, ech and ecl overflow from h'ffff to h'0000, the ovh flag is set to 1 in eccsr, the ech and ecl count values each return to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. 2. 8-bit event counter operation when bit ch2 is set to 1 in eccsr, ech and ecl operate as independent 8-bit event counters. figure 9.21 shows an example of the software processing when ech and ecl are used as 8-bit event counters. section 9 timers rev. 6.00 aug 04, 2006 page 311 of 626 rej09b0144-0600 start end set ch2 to 1 clear cueh, cuel, crch, and crcl to 0 clear ovh, ovl to 0 set cueh, cuel, crch, and crcl to 1 figure 9.21 example of software processing when using ech and ecl as 8-bit event counters ech and ecl can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9.20. the 8-bit event counter operating clock source is asynchronous event input from the aevh pin for ech, and asynchronous event input from the aevl pin for ecl. when the next clock is input after the ech count value reaches h'ff, ech overflows, the ovh flag is set to 1 in eccsr, the ech count value returns to h'00, and counting up is restarted. similarly, when the next clock is input after the ecl count value reaches h'ff, ecl overflows, the ovl flag is set to 1 in eccsr, the ecl count value returns to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. 9.7.4 asynchronous event counter operation modes asynchronous event counter operation modes are shown in table 9.21. table 9.21 asynchronous event counter operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby eccsr reset functions functions held * functions functions held * held ech reset functions functions functions * functions functions functions * halted ecl reset functions functions functions * functions functions functions * halted note: * when an asynchronous external event is input, the counter increments but the counter overflow h/l flags are not affected. section 9 timers rev. 6.00 aug 04, 2006 page 312 of 626 rej09b0144-0600 9.7.5 application notes 1. when reading the values in ech and ecl, the correct value will not be returned if the event counter increments during the read operation. therefore, if the counter is being used in the 8- bit mode, clear bits cueh and cuel in eccsr to 0 before reading ech or ecl. if the counter is being used in the 16-bit mode, clear cuel only to 0 before reading ech or ecl. 2. in the h8/3827r group, if the internal power supply step-down circuit is not used, the maximum clock frequency to be input to the aevh and aevl pins is 16 mhz when vcc = 4.5 to 5.5 v, 10 mhz when vcc = 2.7 to 5.5 v, and 4 mhz when vcc = 1.8 to 5.5 v. if the internal power step-down circuit is used, the maximum clock frequency to be input is 10 mhz when vcc = 2.7 to 5.5 v, and 4 mhz when vcc = 1.8 to 5.5 v. in the h8/3827s group, the maximum clock frequency to be input is 10 mhz when vcc = 2.7 to 3.6 v, and 4 mhz when vcc = 1.8 to 3.6 v. in the h8/38327 group and h8/38427 group, the maximum clock frequency to be input is 16 mhz. in addition, ensure that the high and low widths of the clock are at least 32 ns. the duty cycle is immaterial. section 9 timers rev. 6.00 aug 04, 2006 page 313 of 626 rej09b0144-0600 mode maximum aevh/aevl pin input clock frequency 16-bit mode 8-bit mode active (high-speed), sleep (high-speed) h8/3827r group ? internal step-down circuit not used v cc = 4.5 to 5.5 v/16 mhz v cc = 2.7 to 5.5 v/10 mhz v cc = 1.8 to 5.5 v/4 mhz ? internal step-down circuit used v cc = 2.7 to 5.5 v/10 mhz v cc = 1.8 to 5.5 v/4 mhz h8/3827s group v cc = 2.7 to 3.6 v/10 mhz v cc = 1.8 to 3.6 v/4 mhz h8/38327 group v cc = 2.7 to 5.5 v/16 mhz h8/38427 group v cc = 4.5 to 5.5 v/16 mhz v cc = 2.7 to 5.5 v/10 mhz 8-bit mode active (medium-speed), sleep (medium-speed) ( /16) ( /32) ( /64) f osc = 1 mhz to 16 mhz ( /128) 2 f osc f osc 1/2 f osc 1/4 f osc 8-bit mode watch, subactive, subsleep, standby ( w/2) ( w/4) w = 32.768 khz or 38.4 khz ( w/8) 1000 khz 500 khz 250 khz 3. when aec uses with 16-bit mode, set cueh in eccsr to ?1? first, set crch in eccsr to ?1? second, or set both cueh and crch to ?1? at same time before clock entry. while aec is operating on 16-bit mode, do not change cueh. otherwise, ech will be miscounted up. also, to reset the counter, clear crch and crcl to 0 simultaneously or clear crcl and crch to 0 sequentially, in that order. section 9 timers rev. 6.00 aug 04, 2006 page 314 of 626 rej09b0144-0600 section 10 serial communication interface rev. 6.00 aug 04, 2006 page 315 of 626 rej09b0144-0600 section 10 serial communication interface 10.1 overview this lsi is provided with two serial communication interfaces, sci3-1 and sci3-2. these two scis have identical functions. in this manual, the generic term sci3 is used to refer to both scis. serial communication interface 3 (sci3) can carry out serial data communication in either asynchronous or synchronous mode. it is also provided with a multiprocessor communication function that enables serial data to be transferred among processors. 10.1.1 features features of sci3 are listed below. ? choice of asynchronous or synchronous mode for serial data communication ? asynchronous mode serial data communication is performed asynchronously, with synchronization provided character by character. in this mode, serial data can be exchanged with standard asynchronous communication lsis such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). a multiprocessor communication function is also provided, enabling serial data communication among processors. there is a choice of 16 data transfer formats. data length 7, 8, 5 bits stop bit length 1 or 2 bits parity even, odd, or none multiprocessor bit ?1? or ?0? receive error detection parity, overrun, and framing errors break detection break detected by reading the rxd 3x pin level directly when a framing error occurs section 10 serial communication interface rev. 6.00 aug 04, 2006 page 316 of 626 rej09b0144-0600 ? synchronous mode serial data communication is synchronized with a clock. in his mode, serial data can be exchanged with another lsi that has a synchronous communication function. data length 8 bits receive error detection overrun errors ? full-duplex communication separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. the transmission and reception units are both double-buffered, allowing continuous transmission and reception. ? on-chip baud rate generator, allowing any desired bit rate to be selected ? choice of an internal or external clock as the transmit/receive clock source ? six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error section 10 serial communication interface rev. 6.00 aug 04, 2006 page 317 of 626 rej09b0144-0600 10.1.2 block diagram figure 10.1 shows a block diagram of sci3. clock txd rxd sck brr smr scr3 ssr tdr rdr tsr rsr spcr transmit/receive control circuit internal data bus legend: rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: spcr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter serial port control register interrupt request (tei, txi, rxi, eri) 3x internal clock ( /64, /16, w /2, ) external clock brc baud rate generator figure 10.1 sci3 block diagram section 10 serial communication interface rev. 6.00 aug 04, 2006 page 318 of 626 rej09b0144-0600 10.1.3 pin configuration table 10.1 shows the sci3 pin configuration. table 10.1 pin configuration name abbr. i/o function sci3 clock sck 3x i/o sci3 clock input/output sci3 receive data input rxd 3x input sci3 receive data input sci3 transmit data output txd 3x output sci3 transmit data output 10.1.4 register configuration table 10.2 shows the sci3 register configuration. table 10.2 registers name abbr. r/w initial value address serial mode register smr r/w h'00 h'ffa8/ff98 bit rate register brr r/w h'ff h'ffa9/ff99 serial control register 3 scr3 r/w h'00 h'ffaa/ff9a transmit data register tdr r/w h'ff h'ffab/ff9b serial data register ssr r/w h'84 h'ffac/ff9c receive data register rdr r h'00 h'ffad/ff9d transmit shift register tsr protected ? ? receive shift register rsr protected ? ? bit rate counter brc protected ? ? clock stop register 1 ckstpr1 r/w h'ff h'fffa serial port control register spcr r/w h'c0 h'ff91 section 10 serial communication interface rev. 6.00 aug 04, 2006 page 319 of 626 rej09b0144-0600 10.2 register descriptions 10.2.1 receive shift register (rsr) bit read/write 7 ? 6 ? 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? rsr is a register used to receive serial data. serial data input to rsr from the rxd 3x pin is set in the order in which it is received, starting from the lsb (bit 0), and converted to parallel data. when one byte of data is received, it is transferred to rdr automatically. rsr cannot be read or written directly by the cpu. 10.2.2 receive data register (rdr) bit initial value read/write 7 rdr7 0 r 6 rdr6 0 r 5 rdr5 0 r 4 rdr4 0 r 3 rdr3 0 r 0 rdr0 0 r 2 rdr2 0 r 1 rdr1 0 r rdr is an 8-bit register that stores received serial data. when reception of one byte of data is finished, the received data is transferred from rsr to rdr, and the receive operation is completed. rsr is then able to receive data. rsr and rdr are double-buffered, allowing consecutive receive operations. rdr is a read-only register, and cannot be written by the cpu. rdr is initialized to h'00 upon reset, and in standby, module standby or watch mode. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 320 of 626 rej09b0144-0600 10.2.3 transmit shift register (tsr) bit read/write 7 ? 6 ? 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? tsr is a register used to transmit serial data. transmit data is first transferred from tdr to tsr, and serial data transmission is carried out by sending the data to the txd 3x pin in order, starting from the lsb (bit 0). when one byte of data is transmitted, the next byte of transmit data is transferred to tdr, and transmission started, automatically. data transfer from tdr to tsr is not performed if no data has been written to tdr (if bit tdre is set to 1 in the serial status register (ssr)). tsr cannot be read or written directly by the cpu. 10.2.4 transmit data register (tdr) bit initial value read/write 7 tdr7 1 r/w 6 tdr6 1 r/w 5 tdr5 1 r/w 4 tdr4 1 r/w 3 tdr3 1 r/w 0 tdr0 1 r/w 2 tdr2 1 r/w 1 tdr1 1 r/w tdr is an 8-bit register that stores transmit data. when tsr is found to be empty, the transmit data written in tdr is transferred to tsr, and serial data transmission is started. continuous transmission is possible by writing the next transmit data to tdr during tsr serial data transmission. tdr can be read or written by the cpu at any time. tdr is initialized to h'ff upon reset, and in standby, module standby, or watch mode. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 321 of 626 rej09b0144-0600 10.2.5 serial mode register (smr) bit initial value read/write 7 com 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 pm 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w smr is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. smr can be read or written by the cpu at any time. smr is initialized to h'00 upon reset, and in standby, module standby, or watch mode. bit 7: communication mode (com) bit 7 selects whether sci3 operates in asynchronous mode or synchronous mode. bit 7 com description 0 asynchronous mode (initial value) 1 synchronous mode bit 6: character length (chr) bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. in synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting. bit 6 chr description 0 8-bit data/5-bit data * 2 (initial value) 1 7-bit data * 1 /5-bit data * 2 notes: 1. when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. 2. when 5-bit data is selected, set both pe and mp to 1. the three most significant bits (bits 7, 6, and 5) of tdr are not transmitted. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 322 of 626 rej09b0144-0600 bit 5: parity enable (pe) bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. in synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. bit 5 pe description 0 parity bit addition and checking disabled * 2 (initial value) 1 parity bit addition and checking enabled * 1 * 2 notes: 1. when pe is set to 1, even or odd parity, as designated by bit pm, is added to transmit data before it is sent, and the received parity bit is checked against the parity designated by bit pm. 2. for the case where 5-bit data is selected, see table 10.11. bit 4: parity mode (pm) bit 4 selects whether even or odd parity is to be used for parity addition and checking. the pm bit setting is only valid in asynchronous mode when bit pe is set to 1, enabling parity bit addition and checking. the pm bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled. bit 4 pm description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. 2. when odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 323 of 626 rej09b0144-0600 bit 3: stop bit length (stop) bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. the stop bit setting is only valid in asynchronous mode. when synchronous mode is selected the stop bit setting is invalid since stop bits are not added. bit 3 stop description 01 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2. in transmission, two 1 bits (stop bits) are added at the end of a transmit character. in reception, only the first of the received stop bits is checked, irrespective of the stop bit setting. if the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next transmit character. bit 2: multiprocessor mode (mp) bit 2 enables or disables the multiprocessor communication function. when the multiprocessor communication function is disabled, the parity settings in the pe and pm bits are invalid. the mp bit setting is only valid in asynchronous mode. when synchronous mode is selected the mp bit should be set to 0. for details on the multiprocessor communication function, see section 10.3.4, multiprocessor communication function. bit 2 mp description 0 multiprocessor communication function disabled * (initial value) 1 multiprocessor communication function enabled * note: * for the case where 5-bit data is selected, see table 10.11. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 324 of 626 rej09b0144-0600 bits 1 and 0: clock select 1, 0 (cks1, cks0) bits 1 and 0 choose /64, /16, w/2, or as the clock source for the baud rate generator. for the relation between the clock source, bit rate register setting, and baud rate, see section 10.2.8, bit rate register (brr). bit 1 cks1 bit 0 cks0 description 00 clock (initial value) 01 w/2 clock * 1 / w clock * 2 10 /16 clock 11 /64 clock notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. 10.2.6 serial control register 3 (scr3) bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w scr3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. scr3 can be read or written by the cpu at any time. scr3 is initialized to h'00 upon reset, and in standby, module standby or watch mode. bit 7: transmit interrupt enable (tie) bit 7 selects enabling or disabling of the transmit data empty interrupt request (txi) when transmit data is transferred from the transmit data register (tdr) to the transmit shift register (tsr), and bit tdre in the serial status register (ssr) is set to 1. txi can be released by clearing bit tdre or bit tie to 0. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 325 of 626 rej09b0144-0600 bit 7 tie description 0 transmit data empty interrupt request (txi) disabled (initial value) 1 transmit data empty interrupt request (txi) enabled bit 6: receive interrupt enable (rie) bit 6 selects enabling or disabling of the receive data full interrupt request (rxi) and the receive error interrupt request (eri) when receive data is transferred from the receive shift register (rsr) to the receive data register (rdr), and bit rdrf in the serial status register (ssr) is set to 1. there are three kinds of receive error: overrun, framing, and parity. rxi can be released by clearing bit rdrf or the fer, per, or oer error flag to 0, or by clearing bit rie to 0. bit 6 rie description 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled (initial value) 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled bit 5: transmit enable (te) bit 5 selects enabling or disabling of the start of transmit operation. bit 5 te description 0 transmit operation disabled * 1 (txd pin is i/o port) (initial value) 1 transmit operation enabled * 2 (txd pin is transmit data pin) notes: 1. bit tdre in ssr is fixed at 1. 2. when transmit data is written to tdr in this state, bit tdr in ssr is cleared to 0 and serial data transmission is started. be sure to carry out serial mode register (smr) settings, and setting of bit spc31 or spc32 in spcr, to decide the transmission format before setting bit te to 1. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 326 of 626 rej09b0144-0600 bit 4: receive enable (re) bit 4 selects enabling or disabling of the start of receive operation. bit 4 re description 0 receive operation disabled * 1 (rxd pin is i/o port) (initial value) 1 receive operation enabled * 2 (rxd pin is receive data pin) notes: 1. note that the rdrf, fer, per, and oer flags in ssr are not affected when bit re is cleared to 0, and retain their previous state. 2. in this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. be sure to carry out serial mode register (smr) settings to decide the reception format before setting bit re to 1. bit 3: multiprocessor interrupt enable (mpie) bit 3 selects enabling or disabling of the multiprocessor interrupt request. the mpie bit setting is only valid when asynchronous mode is selected and reception is carried out with bit mp in smr set to 1. the mpie bit setting is invalid when bit com is set to 1 or bit mp is cleared to 0. bit 3 mpie description 0 multiprocessor interrupt request disabled (normal receive operation) (initial value) clearing condition: when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled * note: * receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and oer status flags in ssr is not performed. rxi, eri, and setting of the rdrf, fer, and oer flags in ssr, are disabled until data with the multiprocessor bit set to 1 is received. when a receive character with the multiprocessor bit set to 1 is received, bit mpbr in ssr is set to 1, bit mpie is automatically cleared to 0, and rxi and eri requests (when bits tie and rie in serial control register 3 (scr3) are set to 1) and setting of the rdrf, fer, and oer flags are enabled. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 327 of 626 rej09b0144-0600 bit 2: transmit end interrupt enable (teie) bit 2 selects enabling or disabling of the transmit end interrupt request (tei) if there is no valid transmit data in tdr when msb data is to be sent. bit 2 teie description 0 transmit end interrupt request (tei) disabled (initial value) 1 transmit end interrupt request (tei) enabled * note: * tei can be released by clearing bit tdre to 0 and clearing bit tend to 0 in ssr, or by clearing bit teie to 0. bits 1 and 0: clock enable 1 and 0 (cke1, cke0) bits 1 and 0 select the clock source and enabling or disabling of clock output from the sck 3x pin. the combination of cke1 and cke0 determines whether the sck 3x pin functions as an i/o port, a clock output pin, or a clock input pin. the cke0 bit setting is only valid in case of internal clock operation (cke1 = 0) in asynchronous mode. in synchronous mode, or when external clock operation is used (cke1 = 1), bit cke0 should be cleared to 0. after setting bits cke1 and cke0, set the operating mode in the serial mode register (smr). for details on clock source selection, see table 10.9 in 10.3.1, overview. description bit 1 cke1 bit 0 cke0 communication mode clock source sck 3x pin function 0 0 asynchronous internal clock i/o port * 1 synchronous internal clock serial clock output * 1 0 1 asynchronous internal clock clock output * 2 synchronous reserved 1 0 asynchronous external clock clock input * 3 synchronous external clock serial clock input 1 1 asynchronous reserved synchronous reserved notes: 1. initial value 2. a clock with the same frequency as the bit rate is output. 3. input a clock with a frequency 16 times the bit rate. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 328 of 626 rej09b0144-0600 10.2.7 serial status register (ssr) bit initial value read/write note: * only a write of 0 for flag clearing is possible. 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 oer 0 r/(w) 4 fer 0 r/(w) 3 per 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpbr 0 r ***** ssr is an 8-bit register containing status flags that indicate the operational status of sci3, and multiprocessor bits. ssr can be read or written by the cpu at any time, but only a write of 1 is possible to bits tdre, rdrf, oer, per, and fer. in order to clear these bits by writing 0, 1 must first be read. bits tend and mpbr are read-only bits, and cannot be modified. ssr is initialized to h'84 upon reset, and in standby, module standby, or watch mode. bit 7: transmit data register empty (tdre) bit 7 indicates that transmit data has been transferred from tdr to tsr. bit 7 tdre description 0 transmit data written in tdr has not been transferred to tsr clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmit data has not been written to tdr, or transmit data written in tdr has been transferred to tsr setting conditions: when bit te in scr3 is cleared to 0 when data is transferred from tdr to tsr (initial value) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 329 of 626 rej09b0144-0600 bit 6: receive data register full (rdrf) bit 6 indicates that received data is stored in rdr. bit 6 rdrf description 0 there is no receive data in rdr (initial value) clearing conditions: after reading rdrf = 1, cleared by writing 0 to rdrf when rdr data is read by an instruction 1 there is receive data in rdr setting condition: when reception ends normally and receive data is transferred from rsr to rdr note: if an error is detected in the receive data, or if the re bit in scr3 has been cleared to 0, rdr and bit rdrf are not affected and retain their previous state. note that if data reception is completed while bit rdrf is still set to 1, an overrun error (oer) will result and the receive data will be lost. bit 5: overrun error (oer) bit 5 indicates that an overrun error has occurred during reception. bit 5 oer description 0 reception in progress or completed * 1 (initial value) clearing condition: after reading oer = 1, cleared by writing 0 to oer 1 an overrun error has occurred during reception * 2 setting condition: when reception is completed with rdrf set to 1 notes: 1. when bit re in scr3 is cleared to 0, bit oer is not affected and retains its previous state. 2. rdr retains the receive data it held before the overrun error occurred, and data received after the error is lost. reception cannot be continued with bit oer set to 1, and in synchronous mode, transmission cannot be continued either. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 330 of 626 rej09b0144-0600 bit 4: framing error (fer) bit 4 indicates that a framing error has occurred during reception in asynchronous mode. bit 4 fer description 0 reception in progress or completed * 1 (initial value) clearing condition: after reading fer = 1, cleared by writing 0 to fer 1 a framing error has occurred during reception setting condition: when the stop bit at the end of the receive data is checked for a value of 1 at the end of reception, and the stop bit is 0 * 2 notes: 1. when bit re in scr3 is cleared to 0, bit fer is not affected and retains its previous state. 2. note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. when a framing error occurs the receive data is transferred to rdr but bit rdrf is not set. reception cannot be continued with bit fer set to 1. in synchronous mode, neither transmission nor reception is possible when bit fer is set to 1. bit 3: parity error (per) bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. bit 3 per description 0 reception in progress or completed * 1 (initial value) clearing condition: after reading per = 1, cleared by writing 0 to per 1 a parity error has occurred during reception * 2 setting condition: when the number of 1 bits in the receive data plus parity bit does not match the parity designated by bit pm in the serial mode register (smr) notes: 1. when bit re in scr3 is cleared to 0, bit per is not affected and retains its previous state. 2. receive data in which it a parity error has occurred is still transferred to rdr, but bit rdrf is not set. reception cannot be continued with bit per set to 1. in synchronous mode, neither transmission nor reception is possible when bit fer is set to 1. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 331 of 626 rej09b0144-0600 bit 2: transmit end (tend) bit 2 indicates that bit tdre is set to 1 when the last bit of a transmit character is sent. bit 2 is a read-only bit and cannot be modified. bit 2 tend description 0 transmission in progress clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmission ended (initial value) setting conditions: when bit te in scr3 is cleared to 0 when bit tdre is set to 1 when the last bit of a transmit character is sent bit 1: multiprocessor bit receive (mpbr) bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. bit 1 is a read-only bit and cannot be modified. bit 1 mpbr description 0 data in which the multiprocessor bit is 0 has been received * (initial value) 1 data in which the multiprocessor bit is 1 has been received note: * when bit re is cleared to 0 in scr3 with the multiprocessor format, bit mpbr is not affected and retains its previous state. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 332 of 626 rej09b0144-0600 bit 0: multiprocessor bit transfer (mpbt) bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous mode. the bit mpbt setting is invalid when synchronous mode is selected, when the multiprocessor communication function is disabled, and when not transmitting. bit 0 mpbt description 0 a 0 multiprocessor bit is transmitted (initial value) 1 a 1 multiprocessor bit is transmitted 10.2.8 bit rate register (brr) bit initial value read/write 7 brr7 1 r/w 6 brr6 1 r/w 5 brr5 1 r/w 4 brr4 1 r/w 3 brr3 1 r/w 0 brr0 1 r/w 2 brr2 1 r/w 1 brr1 1 r/w brr is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 of the serial mode register (smr). brr can be read or written by the cpu at any time. brr is initialized to h'ff upon reset, and in standby, module standby, or watch mode. table 10.3 shows examples of brr settings in asynchronous mode. the values shown are for active (high-speed) mode. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 333 of 626 rej09b0144-0600 table 10.3 examples of brr settings for various bit rates (asynchronous mode) (1) osc 32.8 khz 38.4 khz 2 mhz 2.4576 mhz 4 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) n n error (%) 110 ??? ??? 2 21?0.83??? 150 030 2120.16330 2250.16 200 0 2 0 0 155 0.16 3 2 0 ? ? ? 250 ? ? ? 0 124 0 0 153 ?0.26 0 249 0 300 cannot be used, as error exceeds 3% 010 01030.16310 2120.16 600 0 0 0 0 51 0.16 3 0 0 0 103 0.16 1200 ? ? ? 0 25 0.16 2 1 0 0 51 0.16 2400 ? ? ? 0 12 0.16 2 0 0 0 25 0.16 4800 ? ? ? ? ? ? 0 7 0 0 12 0.16 9600 ? ? ? ? ? ? 0 3 0 ? ? ? 19200 ? ? ? ? ? ? 0 1 0 ? ? ? 31250 ? ? ? 0 0 0 ? ? ? 0 1 0 38400 ? ? ? ? ? ? 0 0 0 ? ? ? section 10 serial communication interface rev. 6.00 aug 04, 2006 page 334 of 626 rej09b0144-0600 table 10.3 examples of brr settings for various bit rates (asynchronous mode) (2) osc 10 mhz 16 mhz bit rate (bit/s) n n error (%) n n error (%) 110 2 88 -0.25 2 141 0.03 150 2 64 0.16 2 103 0.16 200 2 48 -0.35 2 77 0.16 250 2 38 0.16 2 62 -0.79 300 ? ? ? 2 51 0.16 600 ? ? ? 2 25 0.16 1200 0 129 0.16 0 207 0.16 2400 0 64 0.16 0 103 0.16 4800 ? ? ? 0 51 0.16 9600 ? ? ? 0 25 0.16 19200 ? ? ? 0 12 0.16 31250 0 4 0 0 7 0 38400 ? ? ? ? ? ? notes: 1. the setting should be made so that the error is not more than 1%. 2. the value set in brr is given by the following equation: osc n = (64 2 2n b) ? 1 where b: bit rate (bit/s) n: baud rate generator brr setting (0 n 255) osc: value of osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.4.) 3. the error in table 10.3 is the value obtained from the following equation, rounded to two decimal places. b (rate obtained from n, n, osc) ? r(bit rate in left-hand column in table 10.3.) error (%) = r (bit rate in left-hand column in table 10.3.) 100 section 10 serial communication interface rev. 6.00 aug 04, 2006 page 335 of 626 rej09b0144-0600 table 10.4 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. table 10.5 shows the maximum bit rate for each frequency. the values shown are for active (high-speed) mode. table 10.5 maximum bit rate for each frequency (asynchronous mode) setting osc (mhz) maximum bit rate (bit/s) n n 0.0384 * 600 0 0 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 10 156250 0 0 16 250000 0 0 * : when smr is set up to cks1 = ?0?, cks0 = ?1?. table 10.6 shows examples of brr settings in synchronous mode. the values shown are for active (high-speed) mode. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 336 of 626 rej09b0144-0600 table 10.6 examples of brr settings for various bit rates (synchronous mode) osc 38.4 khz 2 mhz 4 mhz 10 mhz 16 mhz bit rate (bit/s) n n error n n error n n error n n error n n error 200 0 230 ??? ??? ??? ??? 250 ? ? ? ? ? ? 2 124 0 ? ? ? 3 124 0 300 2 0 0 ??? ??? ??? ??? 500 ??? ??? ??? 2 2490 1k 0 249 0 ? ? ? ? ? ? 2 124 0 2.5k 0 99 0 0 199 0 ? ? ? 2 49 0 5k 0 49 0 0 99 0 0 249 0 2 24 0 10k 0 24 0 0 49 0 0 124 0 0 199 0 25k 090 0190 0490 0790 50k 040 090 0240 0390 100k ? ? ? 0 4 0 ? ? ? 0 19 0 250k 0 0 0 0 1 0 0 4 0 0 7 0 500k 0 0 0 ? ? ? 0 3 0 1m ??? 0 1 0 blank: cannot be set. ?: a setting can be made, but an error will result. notes: the value set in brr is given by the following equation: osc n = (8 2 2n b) ? 1 where b: bit rate (bit/s) n: baud rate generator brr setting (0 n 255) osc: value of osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.7.) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 337 of 626 rej09b0144-0600 table 10.7 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: 1. w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. w clock in subactive mode and subsleep mode in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. 10.2.9 clock stop register 1 (ckstpr1) ? tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bits relating to sci3 are described here. for details of the other bits, see the sections on the relevant modules. bit 6: sci3-1 module standby mode control (s31ckstp) bit 6 controls setting and clearing of module standby mode for sci31. s31ckstp description 0 sci3-1 is set to module standby mode 1 sci3-1 module standby mode is cleared (initial value) note: all sci31 register is initialized in module standby mode. bit 5: sci3-2 module standby mode control (s32ckstp) bit 5 controls setting and clearing of module standby mode for sci32. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 338 of 626 rej09b0144-0600 s32ckstp description 0 sci3-2 is set to module standby mode 1 sci3-2 module standby mode is cleared (initial value) note: all sci32 register is initialized in module standby mode. 10.2.10 serial port control register (spcr) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 spc32 0 r/w 4 spc31 0 r/w 3 scinv3 0 r/w 0 scinv0 0 r/w 2 scinv2 0 r/w 1 scinv1 0 r/w spcr is an 8-bit readable/writable register that performs rxd 31 , rxd 32 , txd 31 , and txd 32 pin input/output data inversion switching. spcr is initialized to h'c0 by a reset. bits 7 to 6: reserved bits bits 7 to 6 are reserved; they are always read as 1 and cannot be modified. bit 5: p4 2 /txd 32 pin function switch (spc32) this bit selects whether pin p4 2 /txd 32 is used as p4 2 or as txd 32 . bit 5 spc32 description 0 functions as p4 2 i/o pin (initial value) 1 functions as txd 32 output pin * note: * set the te bit in scr3 after setting this bit to 1. bit 4: p3 5 /txd 31 pin function switch (spc31) this bit selects whether pin p3 5 /txd 31 is used as p3 5 or as txd 31 . bit 4 spc31 description 0 functions as p3 5 i/o pin (initial value) 1 functions as txd 31 output pin * note: * set the te bit in scr3 after setting this bit to 1. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 339 of 626 rej09b0144-0600 bit 3: txd 32 pin output data inversion switch bit 3 specifies whether or not txd 32 pin output data is to be inverted. bit 3 scinv3 description 0txd 32 output data is not inverted (initial value) 1txd 32 output data is inverted bit 2: rxd 32 pin input data inversion switch bit 2 specifies whether or not rxd 32 pin input data is to be inverted. bit 2 scinv2 description 0rxd 32 input data is not inverted (initial value) 1rxd 32 input data is inverted bit 1: txd 31 pin output data inversion switch bit 1 specifies whether or not txd 31 pin output data is to be inverted. bit 1 scinv1 description 0txd 31 output data is not inverted (initial value) 1txd 31 output data is inverted bit 0: rxd 31 pin input data inversion switch bit 0 specifies whether or not rxd 31 pin input data is to be inverted. bit 0 scinv0 description 0rxd 31 input data is not inverted (initial value) 1rxd 31 input data is inverted section 10 serial communication interface rev. 6.00 aug 04, 2006 page 340 of 626 rej09b0144-0600 10.3 operation 10.3.1 overview sci3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. the serial mode register (smr) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.8. the clock source for sci3 is determined by bit com in smr and bits cke1 and cke0 in scr3, as shown in table 10.9. 1. synchronous mode ? choice of 5-, 7-, or 8-bit data length ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (the combination of these parameters determines the data transfer format and the character length.) ? framing error (fer), parity error (per), overrun error (oer), and break detection during reception ? choice of internal or external clock as the clock source when internal clock is selected: sci3 operates on the baud rate generator clock, and a clock with the same frequency as the bit rate can be output. when external clock is selected: a clock with a frequency 16 times the bit rate must be input. (the on-chip baud rate generator is not used.) 2. synchronous mode ? data transfer format: fixed 8-bit data length ? overrun error (oer) detection during reception ? choice of internal or external clock as the clock source when internal clock is selected: sci3 operates on the baud rate generator clock, and a serial clock is output. when external clock is selected: the on-chip baud rate generator is not used, and sci3 operates on the input serial clock. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 341 of 626 rej09b0144-0600 table 10.8 smr settings and corresponding data transfer formats smr data transfer format bit 7 com bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multiprocessor bit parity bit stop bit length 0 0 0 0 0 8-bit data no no 1 bit 1 asynchronous mode 2 bits 10 yes1 bit 12 bits 1 0 0 7-bit data no 1 bit 12 bits 10 yes1 bit 12 bits 0 1 0 0 8-bit data yes no 1 bit 12 bits 1 0 5-bit data no 1 bit 12 bits 1 0 0 7-bit data yes 1 bit 12 bits 1 0 5-bit data no yes 1 bit 12 bits 1 * 0 ** synchronous mode 8-bit data no no no * : don?t care section 10 serial communication interface rev. 6.00 aug 04, 2006 page 342 of 626 rej09b0144-0600 table 10.9 smr and scr3 settings and clock source selection smr scr3 bit 7 bit 1 bit 0 transmit/receive clock com cke1 cke0 mode clock source sck 3x pin function 0 0 0 internal i/o port (sck 3x pin not used) 1 outputs clock with same frequency as bit rate 10 asynchronous mode external outputs clock with frequency 16 times bit rate 1 0 0 internal outputs serial clock 10 synchronous mode external inputs serial clock 01 1 10 1 11 1 reserved (do not specify these combinations) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 343 of 626 rej09b0144-0600 3. interrupts and continuous transmission/reception sci3 can carry out continuous reception using rxi and continuous transmission using txi. these interrupts are shown in table 10.10. table 10.10 transmit/receive interrupts interrupt flags interrupt request conditions notes rxi rdrf rie when serial reception is performed normally and receive data is transferred from rsr to rdr, bit rdrf is set to 1, and if bit rie is set to 1 at this time, rxi is enabled and an interrupt is requested. (see figure 10.2(a).) the rxi interrupt routine reads the receive data transferred to rdr and clears bit rdrf to 0. continuous reception can be performed by repeating the above operations until reception of the next rsr data is completed. txi tdre tie when tsr is found to be empty (on completion of the previous transmission) and the transmit data placed in tdr is transferred to tsr, bit tdre is set to 1. if bit tie is set to 1 at this time, txi is enabled and an interrupt is requested. (see figure 10.2(b).) the txi interrupt routine writes the next transmit data to tdr and clears bit tdre to 0. continuous transmission can be performed by repeating the above operations until the data transferred to tsr has been transmitted. tei tend teie when the last bit of the character in tsr is transmitted, if bit tdre is set to 1, bit tend is set to 1. if bit teie is set to 1 at this time, tei is enabled and an interrupt is requested. (see figure 10.2(c).) tei indicates that the next transmit data has not been written to tdr when the last bit of the transmit character in tsr is sent. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 344 of 626 rej09b0144-0600 rdr rsr (reception in progress) rdrf = 0 rxd 3x pin rdr rsr (reception completed, transfer) rdrf 1 (rxi request when rie = 1) rxd 3x pin figure 10.2 (a) rdrf setting and rxi interrupt tdr (next transmit data) tsr (transmission in progress) tdre = 0 txd 3x pin tdr tsr (transmission completed, transfer) tdre 1 (txi request when tie = 1) txd 3x pin figure 10.2 (b) tdre setting and txi interrupt tdr tsr (transmission in progress) tend = 0 txd 3x pin tdr tsr (reception completed) tend 1 (tei request when teie = 1) txd 3x pin figure 10.2 (c) tend setting and tei interrupt section 10 serial communication interface rev. 6.00 aug 04, 2006 page 345 of 626 rej09b0144-0600 10.3.2 operation in asynchronous mode in asynchronous mode, serial communication is performed with synchronization provided character by character. a start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. sci3 has separate transmission and reception units, allowing full-duplex communication. as the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. 1. data transfer format the general data transfer format in asynchronous communication is shown in figure 10.3. serial data start bit 1 bit transmit/receive data parity bit stop bit(s) 5, 7, or 8 bits one transfer data unit (character or frame) 1 bit or none 1 or 2 bits mark state 1 (msb) (lsb) figure 10.3 data format in asynchronous communication in asynchronous communication, the communication line is normally in the mark state (high level). sci3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. one transfer data character consists of a start bit (low level), followed by transmit/receive data (lsb-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. the data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. the format is selected by the settings in the serial mode register (smr). section 10 serial communication interface rev. 6.00 aug 04, 2006 page 346 of 626 rej09b0144-0600 table 10.11 data transfer formats (asynchronous mode) 1 chr 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 pe mp stop 2 3 4 5 8-bit data serial data transfer format and frame length smr stop s 6 7 8 9 10 11 12 8-bit data s 7-bit data stop stop s stop 7-bit data s stop stop 5-bit data s stop 5-bit data s stop stop 8-bit data p s stop 8-bit data p s stop stop 8-bit data mpb s stop 8-bit data mpb s stop stop 7-bit data p stop s stop 7-bit data stop s 5-bit data stop p p p s 5-bit data stop stop s legend: s: stop: p: mpb: start bit stop bit parity bit multiprocessor bit stop 7-bit data stop s 7-bit data stop mpb mpb s section 10 serial communication interface rev. 6.00 aug 04, 2006 page 347 of 626 rej09b0144-0600 2. clock either an internal clock generated by the baud rate generator or an external clock input at the sck 3x pin can be selected as the sci3 transmit/receive clock. the selection is made by means of bit com in smr and bits sce1 and cke0 in scr3. see table 10.9 for details on clock source selection. when an external clock is input at the sck 3x pin, the clock frequency should be 16 times the bit rate. when sci3 operates on an internal clock, the clock can be output at the sck 3x pin. in this case the frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises at the center of each bit of transmit/receive data, as shown in figure 10.4. 1 character (1 frame) 0 d0d1d2d3d4d5d6d70/1 1 1 clock serial data figure 10.4 phase relationship between output clock and transfer data (asynchronous mode) (8-bit data, parity, 2 stop bits) 3. data transfer operations sci3 initialization: before data is transferred on sci3, bits te and re in scr3 must first be cleared to 0, and then sci3 must be initialized as follows. note: if the operation mode or data transfer format is changed, bits te and re must first be cleared to 0. when bit te is cleared to 0, bit tdre is set to 1. note that the rdrf, per, fer, and oer flags and the contents of rdr are retained when re is cleared to 0. when an external clock is used in asynchronous mode, the clock should not be stopped during operation, including initialization. when an external clock is used in synchronous mode, the clock should not be supplied during operation, including initialization. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 348 of 626 rej09b0144-0600 figure 10.5 shows an example of a flowchart for initializing sci3. start end clear bits te and re to 0 in scr3 1 2 3 set bits cke1 and cke0 set data transfer format in smr set bits spc31 and spc32 to 1 in spcr set value in brr no wait yes 4 set bits tie, rie, mpie, and teie in scr3, and set bits re and te to 1 in pmr7 has 1-bit period elapsed? set clock selection in scr3. be sure to clear the other bits to 0. if clock output is selected in asynchronous mode, the clock is output immediately after setting bits cke1 and cke0. if clock output is selected for reception in synchronous mode, the clock is output immediately after bits cke1, cke0, and re are set to 1. set the data transfer format in the serial mode register (smr). write the value corresponding to the transfer rate in brr. this operation is not necessary when an external clock is selected. wait for at least one bit period, then set bits tie, rie, mpie, and teie in scr3, and set bits re and te to 1 in pmr7. setting bits te and re enables the txd3x and rxd3x pins to be used. in asynchronous mode the mark state is established when transmitting, and the idle state waiting for a start bit when receiving. 1. 2. 3. 4. figure 10.5 example of sci3 initialization flowchart section 10 serial communication interface rev. 6.00 aug 04, 2006 page 349 of 626 rej09b0144-0600 transmitting: figure 10.6 shows an example of a flowchart for data transmission. this procedure should be followed for data transmission after initializing sci3. start end read bit tdre in ssr sets bits spc31 and spc32 to 1 in spcr 1 2 3 write transmit data to tdr read bit tend in ssr set pdr = 0, pcr = 1 clear bit te to 0 in scr3 no tdre = 1? yes continue data transmission? no tend = 1? no yes yes yes no break output? read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. (after the te bit is set to 1, one frame of 1s is output, then transmission is possible.) when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. if a break is to be output when data transmission ends, set the port pcr to 1 and clear the port pdr to 0, then clear bit te in scr3 to 0. 1. 2. 3. figure 10.6 example of data transmission flowchart (asynchronous mode) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 350 of 626 rej09b0144-0600 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. serial data is transmitted from the txd3x pin using the relevant data transfer format in table 10.11. when the stop bit is sent, sci3 checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and when the stop bit has been sent, starts transmission of the next frame. if bit tdre is set to 1, bit tend in ssr bit is set to 1the mark state, in which 1s are transmitted, is established after the stop bit has been sent. if bit teie in scr3 is set to 1 at this time, a tei request is made. figure 10.12 shows an example of the operation when transmitting in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mar k state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi request tdre cleared to 0 user processing data written to tdr txi request tei request figure 10.7 example of operation when transmitting in asynchronous mode (8-bit data, parity, 1 stop bit) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 351 of 626 rej09b0144-0600 receiving: figure 10.8 shows an example of a flowchart for data reception. this procedure should be followed for data reception after initializing sci3. start end read bits oer, per, fer in ssr 1 2 3 4 read bit rdrf in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer + per + fer = 1? no rdrf = 1? yes continue data reception? no no yes receive error processing (a) read bits oer, per, and fer in the serial status register (ssr) to determine if there is an error. if a receive error has occurred, execute receive error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data reception, finish reading of bit rdrf and rdr before receiving the stop bit of the current frame. when the data in rdr is read, bit rdrf is cleared to 0 automatically. 1. 2. 3. figure 10.8 example of data reception flowchart (asynchronous mode) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 352 of 626 rej09b0144-0600 start receive error processing end of receive error processing 4 clear bits oer, per, fer to 0 in ssr yes oer = 1? yes yes fer = 1? break? yes per = 1? no no no no overrun error processing framing error processing (a) parity error processing if a receive error has occurred, read bits oer, per, and fer in ssr to identify the error, and after carrying out the necessary error processing, ensure that bits oer, per, and fer are all cleared to 0. reception cannot be resumed if any of these bits is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd 3x pin. 4. figure 10.8 example of data reception flowchart (asynchronous mode) (cont) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 353 of 626 rej09b0144-0600 sci3 operates as follows when receiving data. sci3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. reception is carried out in accordance with the relevant data transfer format in table 10.11. the received data is first placed in rsr in lsb-to-msb order, and then the parity bit and stop bit(s) are received. sci3 then carries out the following checks. ? parity check sci3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit pm in the serial mode register (smr). ? stop bit check sci3 checks that the stop bit is 1. if two stop bits are used, only the first is checked. ? status check sci3 checks that bit rdrf is set to 0, indicating that the receive data can be transferred from rsr to rdr. if no receive error is found in the above checks, bit rdrf is set to 1, and the receive data is stored in rdr. if bit rie is set to 1 in scr3, an rxi interrupt is requested. if the error checks identify a receive error, bit oer, per, or fer is set to 1 depending on the kind of error. bit rdrf retains its state prior to receiving the data. if bit rie is set to 1 in scr3, an eri interrupt is requested. table 10.12 shows the conditions for detecting a receive error, and receive data processing. note: no further receive operations are possible while a receive error flag is set. bits oer, fer, per, and rdrf must therefore be cleared to 0 before resuming reception. table 10.12 receive error detection conditions and receive data processing receive error abbr. detection conditions receive data processing overrun error oer when the next date receive operation is completed while bit rdrf is still set to 1 in ssr receive data is not transferred from rsr to rdr framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr parity error per when the parity (odd or even) set in smr is different from that of the received data receive data is transferred from rsr to rdr section 10 serial communication interface rev. 6.00 aug 04, 2006 page 354 of 626 rej09b0144-0600 figure 10.9 shows an example of the operation when receiving in asynchronous mode. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1 d0 d1 d7 0/1 1 0 1 0 d0 d1 d7 0/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 start bit detected eri request in response to framing error figure 10.9 example of operation when receiving in asynchronous mode (8-bit data, parity, 1 stop bit) 10.3.3 operation in synchronous mode in synchronous mode, sci3 transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. sci3 has separate transmission and reception units, allowing full-duplex communication with a shared clock. as the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 355 of 626 rej09b0144-0600 1. data transfer format the general data transfer format in asynchronous communication is shown in figure 10.10. serial clock serial data note: * high level except in continuous transmission/reception lsb msb * * bit 1 bit 0 bit 2 bit 3 bit 4 8 bits one transfer data unit (character or frame) bit 5 bit 6 bit 7 don't care don't care figure 10.10 data format in synchronous communication in synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. data confirmation is guaranteed at the rising edge of the serial clock. one transfer data character begins with the lsb and ends with the msb. after output of the msb, the communication line retains the msb state. when receiving in synchronous mode, sci3 latches receive data at the rising edge of the serial clock. the data transfer format uses a fixed 8-bit data length. parity and multiprocessor bits cannot be added. 2. clock either an internal clock generated by the baud rate generator or an external clock input at the sck 3x pin can be selected as the sci3 serial clock. the selection is made by means of bit com in smr and bits cke1 and cke0 in scr3. see table 10.9 for details on clock source selection. when sci3 operates on an internal clock, the serial clock is output at the sck 3x pin. eight pulses of the serial clock are output in transmission or reception of one character, and when sci3 is not transmitting or receiving, the clock is fixed at the high level. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 356 of 626 rej09b0144-0600 3. data transfer operations sci3 initialization: data transfer on sci3 first of all requires that sci3 be initialized as described in 10.3.2.3. sci3 initialization, and shown in figure 10.5. transmitting: figure 10.11 shows an example of a flowchart for data transmission. this procedure should be followed for data transmission after initializing sci3. start end read bit tdre in ssr sets bits spc31 and spc32 to 1 in spcr 1 2 write transmit data to tdr read bit tend in ssr clear bit te to 0 in scr3 no tdre = 1? yes continue data transmission? no tend = 1? yes yes no read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically, the clock is output, and data transmission is started. when clock output is selected, the clock is output and data transmission started when data is written to tdr. when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. 1. 2. figure 10.11 example of data transmission flowchart (synchronous mode) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 357 of 626 rej09b0144-0600 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. when clock output mode is selected, sci3 outputs 8 serial clock pulses. when an external clock is selected, data is output in synchronization with the input clock. serial data is transmitted from the txd3x pin in order from the lsb (bit 0) to the msb (bit 7). when the msb (bit 7) is sent, checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and starts transmission of the next frame. if bit tdre is set to 1, sci3 sets bit tend to 1 in ssr, and after sending the msb (bit 7), retains the msb state. if bit teie in scr3 is set to 1 at this time, a tei request is made. after transmission ends, the sck pin is fixed at the high level. note: transmission is not possible if an error flag (oer, fer, or per) that indicates the data reception status is set to 1. check that these error flags are all cleared to 0 before a transmit operation. figure 10.12 shows an example of the operation when transmitting in synchronous mode. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi request data written to tdr tdre cleared to 0 txi request tei request figure 10.12 example of operation when transmitting in synchronous mode section 10 serial communication interface rev. 6.00 aug 04, 2006 page 358 of 626 rej09b0144-0600 receiving: figure 10.13 shows an example of a flowchart for data reception. this procedure should be followed for data reception after initializing sci3. start end read bit oer in ssr 1 2 3 4 read bit rdrf in ssr overrun error processing 4 clear bit oer to 0 in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer = 1? no rdrf = 1? yes continue data reception? no no yes overrun error processing end of overrun error processing start overrun error processing read bit oer in the serial status register (ssr) to determine if there is an error. if an overrun error has occurred, execute overrun error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data reception, finish reading of bit rdrf and rdr before receiving the msb (bit 7) of the current frame. when the data in rdr is read, bit rdrf is cleared to 0 automatically. if an overrun error has occurred, read bit oer in ssr, and after carrying out the necessary error processing, clear bit oer to 0. reception cannot be resumed if bit oer is set to 1. 1. 2. 3. 4. figure 10.13 example of data reception flowchart (synchronous mode) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 359 of 626 rej09b0144-0600 sci3 operates as follows when receiving data. sci3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. the received data is placed in rsr in lsb-to-msb order. after the data has been received, sci3 checks that bit rdrf is set to 0, indicating that the receive data can be transferred from rsr to rdr. if this check shows that there is no overrun error, bit rdrf is set to 1, and the receive data is stored in rdr. if bit rie is set to 1 in scr3, an rxi interrupt is requested. if the check identifies an overrun error, bit oer is set to 1. bit rdrf remains set to 1. if bit rie is set to 1 in scr3, an eri interrupt is requested. see table 10.12 for the conditions for detecting a receive error, and receive data processing. note: no further receive operations are possible while a receive error flag is set. bits oer, fer, per, and rdrf must therefore be cleared to 0 before resuming reception. figure 10.14 shows an example of the operation when receiving in synchronous mode. serial clock serial data bit 0 bit 7 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi request rdr data read rdre cleared to 0 rxi request eri request in response to overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 10.14 example of operation when receiving in synchronous mode section 10 serial communication interface rev. 6.00 aug 04, 2006 page 360 of 626 rej09b0144-0600 simultaneous transmit/receive: figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. this procedure should be followed for simultaneous transmission/reception after initializing sci3. start end read bit tdre in ssr sets bits spc31 and spc32 to 1 in spcr 1 2 3 4 write transmit data to tdr read bit oer in ssr read bit rdrf in ssr clear bits te and re to 0 in scr3 yes tdre = 1? no oer = 1? no rdrf = 1? yes continue data transmission/reception? no yes no read receive data in rdr yes overrun error processing read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data transmission/reception, finish reading of bit rdrf and rdr before receiving the msb (bit 7) of the current frame. before receiving the msb (bit 7) of the current frame, also read tdre = 1 to confirm that a write can be performed, then write data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically, and when the data in rdr is read, bit rdrf is cleared to 0 automatically. if an overrun error has occurred, read bit oer in ssr, and after carrying out the necessary error processing, clear bit oer to 0. transmis- sion and reception cannot be resumed if bit oer is set to 1. see figure 10.13 for details on overrun error processing. 1. 2. 3. 4. figure 10.15 example of simultaneous data transmission/reception flowchart (synchronous mode) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 361 of 626 rej09b0144-0600 notes: 1. when switching from transmission to simultaneous transmission/reception, check that sci3 has finished transmitting and that bits tdre and tend are set to 1, clear bit te to 0, and then set bits te and re to 1 simultaneously. 2. when switching from reception to simultaneous transmission/reception, check that sci3 has finished receiving, clear bit re to 0, then check that bit rdrf and the error flags (oer, fer, and per) are cleared to 0, and finally set bits te and re to 1 simultaneously. 10.3.4 multiprocessor communication function the multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data). in multiprocessor communication, each receiver is assigned its own id code. the serial communication cycle consists of two cycles, an id transmission cycle in which the receiver is specified, and a data transmission cycle in which the transfer data is sent to the specified receiver. these two cycles are differentiated by means of the multiprocessor bit, 1 indicating an id transmission cycle, and 0, a data transmission cycle. the sender first sends transfer data with a 1 multiprocessor bit added to the id code of the receiver it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the transmit data. when a receiver receives transfer data with the multiprocessor bit set to 1, it compares the id code with its own id code, and if they are the same, receives the transfer data sent next. if the id codes do not match, it skips the transfer data until data with the multiprocessor bit set to 1 is sent again. in this way, a number of processors can exchange data among themselves. figure 10.16 shows an example of communication between processors using the multiprocessor format. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 362 of 626 rej09b0144-0600 sender serial data receiver a (id = 01) (id = 02) receiver b h'01 id transmission cycle (specifying the receiver) data transmission cycle (sending data to the receiver specified buy the id) mpb: multiprocessor bit (mpb = 1) (mpb = 0) h'aa communication line (id = 03) receiver c (id = 04) receiver d figure 10.16 example of inter-processor communication using multiprocessor format (sending data h'aa to receiver a) there is a choice of four data transfer formats. if a multiprocessor format is specified, the parity bit specification is invalid. see table 10.11 for details. for details on the clock used in multiprocessor communication, see section 10.3.2, operation in asynchronous mode. multiprocessor transmitting: figure 10.17 shows an example of a flowchart for multiprocessor data transmission. this procedure should be followed for multiprocessor data transmission after initializing sci3. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 363 of 626 rej09b0144-0600 start end read bit tdre in ssr sets bits spc31 and spc32 to 1 in spcr 1 3 2 set bit mpdt in ssr write transmit data to tdr read bit tend in ssr clear bit te to 0 in scr3 set pdr = 0, pcr = 1 yes tdre = 1? no continue data transmission? no tend = 1? break output? no yes yes no yes read the serial status register (ssr) and check that bit tdre is set to 1, then set bit mpbt in ssr to 0 or 1 and write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. if a break is to be output when data transmission ends, set the port pcr to 1 and clear the port pdr to 0, then clear bit te in scr3 to 0. 1. 2. 3. figure 10.17 example of multiprocessor data transmission flowchart section 10 serial communication interface rev. 6.00 aug 04, 2006 page 364 of 626 rej09b0144-0600 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. serial data is transmitted from the txd pin using the relevant data transfer format in table 10.11. when the stop bit is sent, sci3 checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and when the stop bit has been sent, starts transmission of the next frame. if bit tdre is set to 1 bit tend in ssr bit is set to 1, the mark state, in which 1s are transmitted, is established after the stop bit has been sent. if bit teie in scr3 is set to 1 at this time, a tei request is made. figure 10.18 shows an example of the operation when transmitting using the multiprocessor format. 1 frame start bit start bit transmit data transmit data mpb mpb stop bit stop bit mar k state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi request tdre cleared to 0 user processing data written to tdr txi request tei request figure 10.18 example of operation when transmitting using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit) multiprocessor receiving: figure 10.19 shows an example of a flowchart for multiprocessor data reception. this procedure should be followed for multiprocessor data reception after initializing sci3. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 365 of 626 rej09b0144-0600 start end read bits oer and fer in ssr 2 set bit mpie to 1 in scr3 1 3 4 5 4 read bit rdrf in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer + fer = 1? no rdrf = 1? yes continue data reception? no no yes read bits oer and fer in ssr no own id? yes read bit rdrf in ssr yes oer + fer = 1? no read receive data in rdr no rdrf = 1? yes receive error processing (a) set bit mpie to 1 in scr3. read bits oer and fer in the serial status register (ssr) to determine if there is an error. if a receive error has occurred, execute receive error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr and compare it with this receiver's own id. if the id is not this receiver's, set bit mpie to 1 again. when the rdr data is read, bit rdrf is cleared to 0 automatically. read ssr and check that bit rdrf is set to 1, then read the data in rdr. if a receive error has occurred, read bits oer and fer in ssr to identify the error, and after carrying out the necessary error processing, ensure that bits oer and fer are both cleared to 0. reception cannot be resumed if either of these bits is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd 3x pin. 1. 2. 3. 4. 5. figure 10.19 example of multiprocessor data reception flowchart section 10 serial communication interface rev. 6.00 aug 04, 2006 page 366 of 626 rej09b0144-0600 start receive error processing end of receive error processing clear bits oer and fer to 0 in ssr yes oer = 1? yes yes fer = 1? break? no no no overrun error processing framing error processing (a) figure 10.19 example of multiprocessor data reception flowchart (cont) figure 10.20 shows an example of the operation when receiving using the multiprocessor format. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 367 of 626 rej09b0144-0600 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi request mpie cleared to 0 user processing rdrf cleared to 0 no rxi request rdr retains previous state rdr data read when data is not this receiver's id, bit mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi request mpie cleared to 0 user processing rdrf cleared to 0 rxi request rdrf cleared to 0 rdr data read when data is this receiver's id, reception is continued rdr data read bit mpie set to 1 again figure 10.20 example of operation when receiving using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit) section 10 serial communication interface rev. 6.00 aug 04, 2006 page 368 of 626 rej09b0144-0600 10.4 interrupts sci3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). these interrupts have the same vector address. the various interrupt requests are shown in table 10.13. table 10.13 sci3 interrupt requests interrupt abbr. interrupt request vector address rxi interrupt request initiated by receive data full flag (rdrf) h'0022/h'0024 txi interrupt request initiated by transmit data empty flag (tdre) tei interrupt request initiated by transmit end flag (tend) eri interrupt request initiated by receive error flag (oer, fer, per) each interrupt request can be enabled or disabled by means of bits tie and rie in scr3. when bit tdre is set to 1 in ssr, a txi interrupt is requested. when bit tend is set to 1 in ssr, a tei interrupt is requested. these two interrupts are generated during transmission. the initial value of bit tdre in ssr is 1. therefore, if the transmit data empty interrupt request (txi) is enabled by setting bit tie to 1 in scr3 before transmit data is transferred to tdr, a txi interrupt will be requested even if the transmit data is not ready. also, the initial value of bit tend in ssr is 1. therefore, if the transmit end interrupt request (tei) is enabled by setting bit teie to 1 in scr3 before transmit data is transferred to tdr, a tei interrupt will be requested even if the transmit data has not been sent. effective use of these interrupt requests can be made by having processing that transfers transmit data to tdr carried out in the interrupt service routine. to prevent the generation of these interrupt requests (txi and tei), on the other hand, the enable bits for these interrupt requests (bits tie and teie) should be set to 1 after transmit data has been transferred to tdr. when bit rdrf is set to 1 in ssr, an rxi interrupt is requested, and if any of bits oer, per, and fer is set to 1, an eri interrupt is requested. these two interrupt requests are generated during reception. for further details, see section 3.3, interrupts. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 369 of 626 rej09b0144-0600 10.5 application notes the following points should be noted when using sci3. 1. relation between writes to tdr and bit tdre bit tdre in the serial status register (ssr) is a status flag that indicates that data for serial transmission has not been prepared in tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. when sci3 transfers data from tdr to tsr, bit tdre is set to 1. data can be written to tdr irrespective of the state of bit tdre, but if new data is written to tdr while bit tdre is cleared to 0, the data previously stored in tdr will be lost of it has not yet been transferred to tsr. accordingly, to ensure that serial transmission is performed dependably, you should first check that bit tdre is set to 1, then write the transmit data to tdr once only (not two or more times). 2. operation when a number of receive errors occur simultaneously if a number of receive errors are detected simultaneously, the status flags in ssr will be set to the states shown in table 10.14. if an overrun error is detected, data transfer from rsr to rdr will not be performed, and the receive data will be lost. table 10.14 ssr status flag states and receive data transfer ssr status flags receive data transfer rdrf * oer fer per rsr rdr receive error status 1 100x overrun error 0 010o framing error 0 001o parity error 1 110x overrun error + framing error 1 101x overrun error + parity error 0 011o framing error + parity error 1 111x overrun error + framing error + parity error o : receive data is transferred from rsr to rdr. x : receive data is not transferred from rsr to rdr. note: * bit rdrf retains its state prior to data reception. however, note that if rdr is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, rdrf will be cleared to 0. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 370 of 626 rej09b0144-0600 3. break detection and processing when a framing error is detected, a break can be detected by reading the value of the rxd 3x pin directly. in a break, the input from the rxd 3x pin becomes all 0s, with the result that bit fer is set and bit per may also be set. sci3 continues the receive operation even after receiving a break. note, therefore, that even though bit fer is cleared to 0 it will be set to 1 again. 4. mark state and break detection when bit te is cleared to 0, the txd 3x pin functions as an i/o port whose input/output direction and level are determined by pdr and pcr. this fact can be used to set the txd 3x pin to the mark state, or to detect a break during transmission. to keep the communication line in the mark state (1 state) until bit te is set to 1, set pcr = 1 and pdr = 1. since bit te is cleared to 0 at this time, the txd 3x pin functions as an i/o port and 1 is output. to detect a break, clear bit te to 0 after setting pcr = 1 and pdr = 0. when bit te is cleared to 0, the transmission unit is initialized regardless of the current transmission state, the txd 3x pin functions as an i/o port, and 0 is output from the txd 3x pin. 5. receive error flags and transmit operation (synchronous mode only) when a receive error flag (oer, per, or fer) is set to 1, transmission cannot be started even if bit tdre is cleared to 0. the receive error flags must be cleared to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if bit re is cleared to 0. 6. receive data sampling timing and receive margin in asynchronous mode in asynchronous mode, sci3 operates on a basic clock with a frequency 16 times the transfer rate. when receiving, sci3 performs internal synchronization by sampling the falling edge of the start bit with the basic clock. receive data is latched internally at the 8th rising edge of the basic clock. this is illustrated in figure 10.21. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 371 of 626 rej09b0144-0600 0 7 15 0 7 15 0 internal basic clock receive data (rxd3x) start bit d0 16 clock pulses 8 clock pulses d1 synchronization sampling timing data sampling timing figure 10.21 receive data sampling timing in asynchronous mode consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). 1 d ? 0.5 m ={(0.5 ? 2n ) ? n ? (l ? 0.5) f} 100 [%] ..... equation (1) where m: receive margin (%) n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock frequency deviation substituting 0 for f (absolute value of clock frequency deviation) and 0.5 for d (clock duty) in equation (1), a receive margin of 46.875% is given by equation (2). when d = 0.5 and f = 0, m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% ..... equation (2) however, this is only a computed value, and a margin of 20% to 30% should be allowed when carrying out system design. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 372 of 626 rej09b0144-0600 7. relation between rdr reads and bit rdrf in a receive operation, sci3 continually checks the rdrf flag. if bit rdrf is cleared to 0 when reception of one frame ends, normal data reception is completed. if bit rdrf is set to 1, this indicates that an overrun error has occurred. when the contents of rdr are read, bit rdrf is cleared to 0 automatically. therefore, if bit rdr is read more than once, the second and subsequent read operations will be performed while bit rdrf is cleared to 0. note that, when an rdr read is performed while bit rdrf is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. this is illustrated in figure 10.22. communication line rdrf rdr frame 1 frame 2 frame 3 data 1 data 1 rdr read rdr read data 1 is read at point (a) data 2 data 3 data 2 (a) data 2 is read at point (b) (b) figure 10.22 relation between rdr read timing and data in this case, only a single rdr read operation (not two or more) should be performed after first checking that bit rdrf is set to 1. if two or more reads are performed, the data read the first time should be transferred to ram, etc., and the ram contents used. also, ensure that there is sufficient margin in an rdr read operation before reception of the next frame is completed. to be precise in terms of timing, the rdr read should be completed before bit 7 is transferred in synchronous mode, or before the stop bit is transferred in asynchronous mode. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 373 of 626 rej09b0144-0600 8. transmit and receive operations when making a state transition make sure that transmit and receive operations have completely finished before carrying out state transition processing. 9. switching sck 3x function if pin sck 3x is used as a clock output pin by sci3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock ( ) cycle immediately after it is switched. this can be prevented by either of the following methods according to the situation. a. when an sck 3x function is switched from clock output to non clock-output when stopping data transfer, issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. in this case, bit com in smr should be left 1. the above prevents sck 3x from being used as a general input/output pin. to avoid an intermediate level of voltage from being applied to sck 3x , the line connected to sck 3x should be pulled up to the v cc level via a resistor, or supplied with output from an external device. b. when an sck 3x function is switched from clock output to general input/output when stopping data transfer, (i) issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. (ii) clear bit com in smr to 0 (iii) clear bits cke1 and cke0 in scr3 to 0 note that special care is also needed here to avoid an intermediate level of voltage from being applied to sck 3x . 10. setup at subactive or subsleep mode at subactive or subsleep mode, sci3 becomes possible use only at cpu clock is w/2. section 10 serial communication interface rev. 6.00 aug 04, 2006 page 374 of 626 rej09b0144-0600 section 11 14-bit pwm rev. 6.00 aug 04, 2006 page 375 of 626 rej09b0144-0600 section 11 14-bit pwm 11.1 overview this lsi is provided with a 14-bit pwm (pulse width modulator) on-chip, which can be used as a d/a converter by connecting a low-pass filter. 11.1.1 features features of the 14-bit pwm are as follows. ? choice of two conversion periods any of the following four conversion periods can be chosen: ? 131,072/ , with a minimum modulation width of 8/ (pwcr1 = 1, pwcr0 = 1) ? 65,536/ , with a minimum modulation width of 4/ (pwcr1 = 1, pwcr0 = 0) ? 32,768/ , with a minimum modulation width of 2/ (pwcr1 = 0, pwcr0 = 1) ? 16,384/ , with a minimum modulation width of 1/ (pwcr1 = 0, pwcr0 = 0) ? pulse division method for less ripple ? use of module standby mode enables this module to be placed in standby mode independently when not used. section 11 14-bit pwm rev. 6.00 aug 04, 2006 page 376 of 626 rej09b0144-0600 11.1.2 block diagram figure 11.1 shows a block diagram of the 14-bit pwm. internal data bus pwdrl pwdru pwcr pwm waveform generator /2 /4 /8 /16 legend: pwdrl: pwdru: pwcr: pwm data register l pwm data register u pwm control register pwm figure 11.1 block diagram of the 14 bit pwm 11.1.3 pin configuration table 11.1 shows the output pin assigned to the 14-bit pwm. table 11.1 pin configuration name abbr. i/o function pwm output pin pwm output pulse-division pwm waveform output section 11 14-bit pwm rev. 6.00 aug 04, 2006 page 377 of 626 rej09b0144-0600 11.1.4 register configuration table 11.2 shows the register configuration of the 14-bit pwm. table 11.2 register configuration name abbr. r/w initial value address pwm control register pwcr w h'fc h'ffd0 pwm data register u pwdru w h'c0 h'ffd1 pwm data register l pwdrl w h'00 h'ffd2 clock stop register 2 ckstpr2 r/w h'ff h'fffb 11.2 register descriptions 11.2.1 pwm control register (pwcr) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 pwcr0 0 w 2 ? 1 ? 1 pwcr1 0 w pwcr is an 8-bit write-only register for input clock selection. upon reset, pwcr is initialized to h'fc. bits 7 to 2: reserved bits bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. section 11 14-bit pwm rev. 6.00 aug 04, 2006 page 378 of 626 rej09b0144-0600 bits 1 and 0: clock select 1 and 0 (pwcr1, pwcr0) bits 1 and 0 select the clock supplied to the 14-bit pwm. these bits are write-only bits; they are always read as 1. bit 1 pwcr1 bit 0 pwcr0 description 0 0 the input clock is /2 (t * = 2/ ) (initial value) the conversion period is 16,384/ , with a minimum modulation width of 1/ 0 1 the input clock is /4 (t * = 4/ ) the conversion period is 32,768/ , with a minimum modulation width of 2/ 1 0 the input clock is /8 (t * = 8/ ) the conversion period is 65,536/ , with a minimum modulation width of 4/ 1 1 the input clock is /16 (t * = 16/ ) the conversion period is 131,072/ , with a minimum modulation width of 8/ note: * period of pwm input clock. 11.2.2 pwm data registers u and l (pwdru, pwdrl) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 pwdru5 0 w 4 pwdru4 0 w 3 pwdru3 0 w 0 pwdru0 0 w 2 pwdru2 0 w 1 pwdru1 0 w pwdru bit initial value read/write 7 pwdrl7 0 w 6 pwdrl6 0 w 5 pwdrl5 0 w 4 pwdrl4 0 w 3 pwdrl3 0 w 0 pwdrl0 0 w 2 pwdrl2 0 w 1 pwdrl1 0 w pwdrl pwdru and pwdrl form a 14-bit write-only register, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. the value written to pwdru and pwdrl gives the total high- level width of one pwm waveform cycle. section 11 14-bit pwm rev. 6.00 aug 04, 2006 page 379 of 626 rej09b0144-0600 when 14-bit data is written to pwdru and pwdrl, the register contents are latched in the pwm waveform generator, updating the pwm waveform generation data. the 14-bit data should always be written in the following sequence: 1. write the lower 8 bits to pwdrl. 2. write the upper 6 bits to pwdru. pwdru and pwdrl are write-only registers. if they are read, all bits are read as 1. upon reset, pwdru and pwdrl are initialized to h'c000. 11.2.3 clock stop register 2 (ckstpr2) ? wdckstp pwckstp ldckstp ??? aeckstp 76543210 1 1111111 ? r/w r/w r/w ??? r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the pwm is described here. for details of the other bits, see the sections on the relevant modules. bit 1: pwm module standby mode control (pwckstp) bit 1 controls setting and clearing of module standby mode for the pwm. pwckstp description 0 pwm is set to module standby mode 1 pwm module standby mode is cleared (initial value) section 11 14-bit pwm rev. 6.00 aug 04, 2006 page 380 of 626 rej09b0144-0600 11.3 operation 11.3.1 operation when using the 14-bit pwm, set the registers in the following sequence. 1. set bit pwm in port mode register 3 (pmr3) to 1 so that pin p3 0 /pwm is designated for pwm output. 2. set bits pwcr1 and pwcr0 in the pwm control register (pwcr) to select a conversion period of 131,072/ (pwcr1 = 1, pwcr0 = 1), 65,536/ (pwcr1 = 1, pwcr0 = 0), 32,768/ (pwcr1 = 0, pwcr0 = 1), or 16,384/ (pwcr1 = 0, pwcr0 = 0). 3. set the output waveform data in pwm data registers u and l (pwdru/l). be sure to write in the correct sequence, first pwdrl then pwdru. when data is written to pwdru, the data in these registers will be latched in the pwm waveform generator, updating the pwm waveform generation in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 11.2. the total of the high-level pulse widths during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be represented as follows. t h = (data value in pwdru and pwdrl + 64) t /2 where t is the pwm input clock period: 2/ (pwcr = h'0), 4/ (pwcr = h'1), 8/ (pwcr = h'2), or 16/ (pwcr = h'3). example: settings in order to obtain a conversion period of 32,768 s: when pwcr1 = 0 and pwcr0 = 0, the conversion period is 16,384/ , so must be 0.5 mhz. in this case, tfn = 512 s, with 1/ (resolution) = 2.0 s. when pwcr1 = 0 and pwcr0 = 1, the conversion period is 32,768/ , so must be 1 mhz. in this case, tfn = 512 s, with 2/ (resolution) = 2.0 s. when pwcr1 = 1 and pwcr0 = 0, the conversion period is 65,536/ , so must be 2 mhz. in this case, tfn = 512 s, with 4/ (resolution) = 2.0 s. accordingly, for a conversion period of 32,768 s, the system clock frequency ( ) must be 0.5 mhz, 1 mhz, or 2 mhz. section 11 14-bit pwm rev. 6.00 aug 04, 2006 page 381 of 626 rej09b0144-0600 1 conversion period t f1 t f2 t f63 t f64 t h1 t h2 t h3 t h63 t h64 t = t + t + t + t = t = t h h1 h2 h3 h64 ..... t f1 f2 f3 ..... = t f64 figure 11.2 pwm output waveform 11.3.2 pwm operation modes pwm operation modes are shown in table 11.3. table 11.3 pwm operation modes operation mode reset active sleep watch subactive subsleep standby module standby pwcr reset functions functions held held held held held pwdru reset functions functions held held held held held pwdrl reset functions functions held held held held held section 11 14-bit pwm rev. 6.00 aug 04, 2006 page 382 of 626 rej09b0144-0600 section 12 a/d converter rev. 6.00 aug 04, 2006 page 383 of 626 rej09b0144-0600 section 12 a/d converter 12.1 overview this lsi includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 8 channels of analog input. 12.1.1 features the a/d converter has the following features. ? 10-bit resolution ? eight input channels ? conversion time: approx. 12.4 s per channel (at 5 mhz operation) ? built-in sample-and-hold function ? interrupt requested on completion of a/d conversion ? a/d conversion can be started by external trigger input ? use of module standby mode enables this module to be placed in standby mode independently when not used. section 12 a/d converter rev. 6.00 aug 04, 2006 page 384 of 626 rej09b0144-0600 12.1.2 block diagram figure 12.1 shows a block diagram of the a/d converter. internal data bus amr adsr adrrh adrrl control logic + ? com- parator an an an an an an an an adtrg av av cc ss multiplexer reference voltage irrad av cc av ss 0 1 2 3 4 5 6 7 legend: amr: adsr: adrr: irrad: a/d mode register a/d start register a/d result register a/d conversion end interrupt request flag figure 12.1 block diagram of the a/d converter section 12 a/d converter rev. 6.00 aug 04, 2006 page 385 of 626 rej09b0144-0600 12.1.3 pin configuration table 12.1 shows the a/d converter pin configuration. table 12.1 pin configuration name abbr. i/o function analog power supply av cc input power supply and reference voltage of analog part analog ground av ss input ground and reference voltage of analog part analog input 0 an 0 input analog input channel 0 analog input 1 an 1 input analog input channel 1 analog input 2 an 2 input analog input channel 2 analog input 3 an 3 input analog input channel 3 analog input 4 an 4 input analog input channel 4 analog input 5 an 5 input analog input channel 5 analog input 6 an 6 input analog input channel 6 analog input 7 an 7 input analog input channel 7 external trigger input adtrg input external trigger input for starting a/d conversion 12.1.4 register configuration table 12.2 shows the a/d converter register configuration. table 12.2 register configuration name abbr. r/w initial value address a/d mode register amr r/w h'30 h'ffc6 a/d start register adsr r/w h'7f h'ffc7 a/d result register h adrrh r not fixed h'ffc4 a/d result register l adrrl r not fixed h'ffc5 clock stop register 1 ckstprt1 r/w h'ff h'fffa section 12 a/d converter rev. 6.00 aug 04, 2006 page 386 of 626 rej09b0144-0600 12.2 register descriptions 12.2.1 a/d result registers (adrrh, adrrl) bit 7 6 5 4 3 adrrh adrrl 0 21 76543 0 21 initial value read/write not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r not fixed r ? ? ? ? ? ? ? ? ? ? ? ? adr9 adr8 adr7 adr6 adr5 adr2 adr4 adr3 adr1 adr0 ??? ? ?? adrrh and adrrl together comprise a 16-bit read-only register for holding the results of analog-to-digital conversion. the upper 8 bits of the data are held in adrrh, and the lower 2 bits in adrrl. adrrh and adrrl can be read by the cpu at any time, but the adrrh and adrrl values during a/d conversion are not fixed. after a/d conversion is complete, the conversion result is stored as 10-bit data, and this data is held until the next conversion operation starts. adrrh and adrrl are not cleared on reset. 12.2.2 a/d mode register (amr) bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 5 ? 1 ? 4 ? 1 ? 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w amr is an 8-bit read/write register for specifying the a/d conversion speed, external trigger option, and the analog input pins. upon reset, amr is initialized to h'30. section 12 a/d converter rev. 6.00 aug 04, 2006 page 387 of 626 rej09b0144-0600 bit 7: clock select (cks) bit 7 sets the a/d conversion speed. bit 7 conversion time (active (high-speed) mode) * cks conversion period = 1 mhz = 5 mhz 0 62/ (initial value) 62 s 12.4 s 1 31/ 31 s ? note: * for information on conversion time settings for which operation is guaranteed, see section 15, electrical characteristics. bit 6: external trigger select (trge) bit 6 enables or disables the start of a/d conversion by external trigger input. bit 6 trge description 0 disables start of a/d conversion by external trigger (initial value) 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg * note: * the external trigger ( adtrg ) edge is selected by bit ieg4 of iegr. see 1. irq edge select register (iegr) in section 3.3.2 for details. bits 5 and 4: reserved bits bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. bits 3 to 0: channel select (ch3 to ch0) bits 3 to 0 select the analog input channel. the channel selection should be made while bit adsf is cleared to 0. section 12 a/d converter rev. 6.00 aug 04, 2006 page 388 of 626 rej09b0144-0600 bit 3 ch3 bit 2 ch2 bit 1 ch1 bit 0 ch0 analog input channel 00 ** no channel selected (initial value) 0100an0 0101an1 0110an2 0111an3 1000an4 1001an5 1010an6 1011an7 11 ** setting prohibited note: * don?t care 12.2.3 a/d start register (adsr) bit initial value read/write 7 adsf 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? the a/d start register (adsr) is an 8-bit read/write register for starting and stopping a/d conversion. a/d conversion is started by writing 1 to the a/d start flag (adsf) or by input of the designated edge of the external trigger signal, which also sets adsf to 1. when conversion is complete, the converted data is set in adrrh and adrrl, and at the same time adsf is cleared to 0. section 12 a/d converter rev. 6.00 aug 04, 2006 page 389 of 626 rej09b0144-0600 bit 7: a/d start flag (adsf) bit 7 controls and indicates the start and end of a/d conversion. bit 7 adsf description 0 read: indicates the completion of a/d conversion (initial value) write: stops a/d conversion 1 read: indicates a/d conversion in progress write: starts a/d conversion bits 6 to 0: reserved bits bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 12.2.4 clock stop register 1 (ckstpr1) ? tfckstp tcckstp tackstp s31ckstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the a/d converter is described here. for details of the other bits, see the sections on the relevant modules. bit 4: a/d converter module standby mode control (adckstp) bit 4 controls setting and clearing of module standby mode for the a/d converter. adckstp description 0 a/d converter is set to module standby mode 1 a/d converter module standby mode is cleared (initial value) section 12 a/d converter rev. 6.00 aug 04, 2006 page 390 of 626 rej09b0144-0600 12.3 operation 12.3.1 a/d conversion operation the a/d converter operates by successive approximations, and yields its conversion result as 10- bit data. a/d conversion begins when software sets the a/d start flag (bit adsf) to 1. bit adsf keeps a value of 1 during a/d conversion, and is cleared to 0 automatically when conversion is complete. the completion of conversion also sets bit irrad in interrupt request register 2 (irr2) to 1. an a/d conversion end interrupt is requested if bit ienad in interrupt enable register 2 (ienr2) is set to 1. if the conversion time or input channel needs to be changed in the a/d mode register (amr) during a/d conversion, bit adsf should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 start of a/d conversion by external trigger input the a/d converter can be made to start a/d conversion by input of an external trigger signal. external trigger input is enabled at pin adtrg when bit irq4 in pmr1 is set to 1 and bit trge in amr is set to 1. then when the input signal edge designated in bit ieg4 of interrupt edge select register (iegr) is detected at pin adtrg , bit adsf in adsr will be set to 1, starting a/d conversion. figure 12.2 shows the timing. pin adtrg (when bit ieg4 = 0) adsf a/d conversion figure 12.2 external trigger input timing section 12 a/d converter rev. 6.00 aug 04, 2006 page 391 of 626 rej09b0144-0600 12.3.3 a/d converter operation modes a/d converter operation modes are shown in table 12.3. table 12.3 a/d converter operation modes operation mode reset active sleep watch subactive subsleep standby module standby amr reset functions functions held held held held held adsr reset functions functions held held held held held adrrh held * functions functions held held held held held adrrl held * functions functions held held held held held note: * undefined in a power-on reset. 12.4 interrupts when a/d conversion ends (adsf changes from 1 to 0), bit irrad in interrupt request register 2 (irr2) is set to 1. a/d conversion end interrupts can be enabled or disabled by means of bit ienad in interrupt enable register 2 (ienr2). for further details see section 3.3, interrupts. section 12 a/d converter rev. 6.00 aug 04, 2006 page 392 of 626 rej09b0144-0600 12.5 typical use an example of how the a/d converter can be used is given below, using channel 1 (pin an1) as the analog input channel. figure 12.3 shows the operation timing. 1. bits ch3 to ch0 of the a/d mode register (amr) are set to 0101, making pin an 1 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is complete, bit irrad is set to 1, and the a/d conversion result is stored is stored in adrrh and adrrl. at the same time adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if adsf is set to 1 again afterward, a/d conversion starts and steps 2 to 6 take place. figures 12.4 and 12.5 show flow charts of procedures for using the a/d converter. section 12 a/d converter rev. 6.00 aug 04, 2006 page 393 of 626 rej09b0144-0600 idle a/d conversion (1) idle a/d conversion (2) idle interrupt (irrad) ienad adsf channel 1 (an 1 ) operation state adrrh adrrl set * set * set * read conversion result read conversion result a/d conversion result (1) a/d c onversion result (2) a/d conversion starts note: ( ) indicates instruction execution by software. * figure 12.3 typical a/d converter operation timing section 12 a/d converter rev. 6.00 aug 04, 2006 page 394 of 626 rej09b0144-0600 start set a/d conversion speed and input channel perform a/d conversion? end yes no disable a/d conversion end interrupt start a/d conversion adsf = 0? no yes read adsr read adrrh/adrrl data figure 12.4 flow chart of procedure for using a/d converter (polling by software) section 12 a/d converter rev. 6.00 aug 04, 2006 page 395 of 626 rej09b0144-0600 start set a/d conversion speed and input channels enable a/d conversion end interrupt start a/d conversion a/d conversion end interrupt? yes no end yes no clear bit irrad to 0 in irr2 read adrrh/adrrl data perform a/d conversion? figure 12.5 flow chart of procedure for using a/d converter (interrupts used) section 12 a/d converter rev. 6.00 aug 04, 2006 page 396 of 626 rej09b0144-0600 12.6 application notes 12.6.1 application notes ? data in adrrh and adrrl should be read only when the a/d start flag (adsf) in the a/d start register (adsr) is cleared to 0. ? changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. ? when a/d conversion is started after clearing module standby mode, wait for 10 clock cycles before starting. ? in active mode or sleep mode, analog power supply current (ai stop1 ) flows into the ladder resistance even when the a/d converter is not operating. therefore, if the a/d converter is not used, it is recommended that av cc be connected to the system power supply and the adckstp(a/d converter module standby mode control) bit be cleared to 0 in clock stop register 1 (ckstpr1). 12.6.2 permissible signal source impedance this lsi?s analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k ? or less. this specification is provided to enable the a/d converter?s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k ? , charging may be insufficient and it may not be possible to guarantee a/d conversion precision. however, a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 12.6). when converting a high-speed analog signal, a low- impedance buffer should be inserted. section 12 a/d converter rev. 6.00 aug 04, 2006 page 397 of 626 rej09b0144-0600 12.6.3 influences on absolute precision adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. a/d converter equivalent circuit this lsi 20 pf c in = 15 pf 10 k ? up to 10 k ? low-pass filter c to 0.1 f sensor output impedance sensor input figure 12.6 analog input circuit example section 12 a/d converter rev. 6.00 aug 04, 2006 page 398 of 626 rej09b0144-0600 section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 399 of 626 rej09b0144-0600 section 13 lcd controller/driver 13.1 overview this lsi has an on-chip segment type lcd control circuit, lcd driver, and power supply circuit, enabling it to directly drive an lcd panel. 13.1.1 features 1. features features of the lcd controller/driver are given below. ? display capacity duty cycle internal driver segment external expansion driver static 32 seg 256 seg 1/2 32 seg 128 seg 1/3 32 seg 64 seg 1/4 32 seg 64 seg ? lcd ram capacity 8 bits 32 bytes (256 bits) ? word access to lcd ram ? all eight segment output pins can be used individually as port pins. ? common output pins not used because of the duty cycle can be used for common double- buffering (parallel connection). ? display possible in operating modes other than standby mode ? choice of 11 frame frequencies ? built-in power supply split-resistance, supplying lcd drive power ? use of module standby mode enables this module to be placed in standby mode independently when not used. ? a or b waveform selectable by software section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 400 of 626 rej09b0144-0600 13.1.2 block diagram figure 13.1 shows a block diagram of the lcd controller/driver. /2 to /256 w cl 2 cl 1 seg n, do lpcr lcr lcr2 display timing generator lcd ram (32 bytes) internal data bus 32-bit shift register lcd drive power supply segment driver common data latch common driver m v 1 v 2 v 3 v ss com 1 com 4 seg 32 /cl 1 * seg 31 /cl 2 * seg 30 /do * seg 29 /m * seg 28 seg 1 legend: lpcr: lcd port control register lcr: lcd control register lcr2: lcd control register 2 note: * the external expansion function for lcd segments is not implemented in the h8/38327 group and h8/38427 group. v 0 figure 13.1 block diagram of lcd controller/driver section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 401 of 626 rej09b0144-0600 13.1.3 pin configuration table 13.1 shows the lcd controller/driver pin configuration. table 13.1 pin configuration name abbr. i/o function segment output pins seg 32 to seg 1 output lcd segment drive pins all pins are multiplexed as port pins (setting programmable) common output pins com 4 to com 1 output lcd common drive pins pins can be used in parallel with static or 1/2 duty segment external expansion signal pins * cl 1 output display data latch clock, multiplexed as seg 32 cl 2 output display data shift clock, multiplexed as seg 31 m output lcd alternation signal, multiplexed as seg 29 do output serial display data, multiplexed as seg 30 lcd power supply pins v 0 , v 1 , v 2 , v 3 ? used when a bypass capacitor is connected externally, and when an external power supply circuit is used note: * the external expansion function for lcd segments is not implemented in the h8/38327 group and h8/38427 group. 13.1.4 register configuration table 13.2 shows the register configuration of the lcd controller/driver. table 13.2 lcd controller/driver registers name abbr. r/w initial value address lcd port control register lpcr r/w h'00 h'ffc0 lcd control register lcr r/w h'80 h'ffc1 lcd control register 2 lcr2 r/w h'60 h'ffc2 lcd ram ? r/w undefined h'f740, h'f75f clock stop register 2 ckstpr2 r/w h'ff h'fffb section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 402 of 626 rej09b0144-0600 13.2 register descriptions 13.2.1 lcd port control register (lpcr) bit initial value read/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 4 sgx 0 r/w 3 sgs3 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w lpcr is an 8-bit read/write register which selects the duty cycle and lcd driver pin functions. lpcr is initialized to h'00 upon reset. bits 7 to 5: duty cycle select 1 and 0 (dts1, dts0), common function select (cmx) the combination of dts1 and dts0 selects static, 1/2, 1/3, or 1/4 duty. cmx specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. bit 7 dts1 bit 6 dts0 bit 5 cmx duty cycle common drivers notes 000static com 1 (initial value) do not use com 4 , com 3 , and com 2 . 1com 4 to com 1 com 4 , com 3 , and com 2 output the same waveform as com 1 . 0101/2 dutycom 2 to com 1 do not use com 4 and com 3 . 1com 4 to com 1 com 4 outputs the same waveform as com 3 , and com 2 outputs the same waveform as com 1 . 1001/3 dutycom 3 to com 1 do not use com 4 . 1com 4 to com 1 do not use com 4 . 1101/4 dutycom 4 to com 1 ? 1 section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 403 of 626 rej09b0144-0600 bit 4: expansion signal select (sgx) bit 4 selects whether the seg 32 /cl 1 , seg 31 /cl 2 , seg 30 /do, and seg 29 /m pins are used as segment pins (seg 32 to seg 29 ) or as segment external expansion pins (cl 1 , cl 2 , do, and m). in the h8/38327 group and h8/38427 group this bit should be left at its initial value and not written to. changing the value of this bit may prevent the seg/com signal from operating normally. bit 4 sgx description 0 pins seg 32 to seg 29 * (initial value) 1pins cl 1 , cl 2 , do, m note: * these pins function as ports when the setting of sgs3 to sgs0 is 0000 or 0001. bits 3 to 0: segment driver select 3 to 0 (sgs3 to sgs0) bits 3 to 0 select the segment drivers to be used. the sgx = 0 setting is selected on the h8/38327 and h8/38427. function of pins seg 32 to seg 1 bit 4 sgx bit 3 sgs3 bit 2 sgs2 bit 1 sgs1 bit 0 sgs0 seg 32 to seg 25 seg 24 to seg 17 seg 16 to seg 9 seg 8 to seg 1 notes 00000port port port port (initial value) 0 0 0 1 port port port port 001 * seg port port port 010 * seg seg port port 011 * seg seg seg port 1 *** seg seg seg seg 10000port * 1 port port port **** setting prohibited * : don?t care note: 1. seg 32 to seg 29 are external expansion pins. section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 404 of 626 rej09b0144-0600 13.2.2 lcd control register (lcr) bit initial value read/write 7 ? 1 ? 6 psw 0 r/w 5 act 0 r/w 4 disp 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w lcr is an 8-bit read/write register which performs lcd drive power supply on/off control and display data control, and selects the frame frequency. lcr is initialized to h'80 upon reset. bit 7: reserved bit bit 7 is reserved; it is always read as 1 and cannot be modified. bit 6: lcd drive power supply on/off control (psw) bit 6 can be used to turn the lcd drive power supply off when lcd display is not required in a power-down mode, or when an external power supply is used. when the act bit is cleared to 0, or in standby mode, the lcd drive power supply is turned off regardless of the setting of this bit. bit 6 psw description 0 lcd drive power supply off (initial value) 1 lcd drive power supply on bit 5: display function activate (act) bit 5 specifies whether or not the lcd controller/driver is used. clearing this bit to 0 halts operation of the lcd controller/driver. the lcd drive power supply is also turned off, regardless of the setting of the psw bit. however, register contents are retained. bit 5 act description 0 lcd controller/driver operation halted (initial value) 1 lcd controller/driver operates section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 405 of 626 rej09b0144-0600 bit 4: display data control (disp) bit 4 specifies whether the lcd ram contents are displayed or blank data is displayed regardless of the lcd ram contents. bit 4 disp description 0 blank data is displayed (initial value) 1 lcd ram data is display bits 3 to 0: frame frequency select 3 to 0 (cks3 to cks0) bits 3 to 0 select the operating clock and the frame frequency. in subactive mode, watch mode, and subsleep mode, the system clock ( ) is halted, and therefore display operations are not performed if one of the clocks from /2 to /256 is selected. if lcd display is required in these modes, w, w/2, or w/4 must be selected as the operating clock. frame frequency * 2 bit 3 cks3 bit 2 cks2 bit 1 cks1 bit 0 cks0 operating clock = 2 mhz = 250 khz * 1 0 * 00 w 128 hz * 3 (initial value) 0 * 01 w/2 64 hz * 3 0 * 1 * w/4 32 hz * 3 1000 /2 ? 244 hz 1001 /4 977 hz 122 hz 1010 /8 488 hz 61 hz 1011 /16 244 hz 30.5 hz 1100 /32 122 hz ? 1101 /64 61 hz ? 1110 /128 30.5 hz ? 1111 /256 ? ? * : don?t care notes: 1. this is the frame frequency in active (medium-speed, osc/16) mode when = 2 mhz. 2. when 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 3. this is the frame frequency when w = 32.768 khz. section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 406 of 626 rej09b0144-0600 13.2.3 lcd control register 2 (lcr2) bit initial value read/write 7 lcdab 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 0 r/w 3 cds3 0 r/w 0 cds0 0 r/w 2 cds2 0 r/w 1 cds1 0 r/w lcr2 is an 8-bit read/write register which controls switching between the a waveform and b waveform, and selects the duty cycle of the charge/discharge pulses which control disconnection of the power supply split-resistance from the power supply circuit. lcr2 is initialized to h'60 upon reset. bit 7: a waveform/b waveform switching control (lcdab) bit 7 specifies whether the a waveform or b waveform is used as the lcd drive waveform. bit 7 lcdab description 0 drive using a waveform (initial value) 1 drive using b waveform bits 6 and 5: reserved bits bits 6 and 5 are reserved; they are always read as 1 and cannot be modified. bit 4: reserved bit bit 4 is reserved; it is always read as 0 and must not be written with 1. section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 407 of 626 rej09b0144-0600 bits 3 to 0: charge/discharge pulse duty cycle select (cds3 to cds0) bit 3 cds3 bit 2 cds2 bit 1 cds1 bit 0 cds0 duty cycle notes 00001 fixed high (initial value) 00011/8 00102/8 00113/8 01004/8 01015/8 01106/8 01110 fixed low 10 ** 1/16 11 ** 1/32 * : don?t care bits 3 to 0 select the duty cycle while the power supply split-resistance is connected to the power supply circuit. when a 0 duty cycle is selected, the power supply split-resistance is permanently disconnected from the power supply circuit, so power should be supplied to pins v 1 , v 2 , and v 3 by an external circuit. figure 13.2 shows the waveform of the charge/discharge pulses. the duty cycle is tc/tw. com1 charge/discharge pulses tc tdc t w 1 frame tc: tdc: power supply split-resistance connected power supply split-resistance disconnected figure 13.2 example of a waveform with 1/2 duty and 1/2 bias section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 408 of 626 rej09b0144-0600 13.2.4 clock stop register 2 (ckstpr2) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 aeckstp 1 r/w 0 ldckstp 1 r/w 2 wdckstp 1 r/w 1 pwckstp 1 r/w ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the lcd controller/driver is described here. for details of the other bits, see the sections on the relevant modules. bit 0: lcd controller/driver module standby mode control (ldckstp) bit 0 controls setting and clearing of module standby mode for the lcd controller/driver. bit 0 ldckstp description 0 lcd controller/driver is set to module standby mode 1 lcd controller/driver module standby mode is cleared (initial value) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 409 of 626 rej09b0144-0600 13.3 operation 13.3.1 settings up to lcd display to perform lcd display, the hardware and software related items described below must first be determined. 1. hardware settings a. using 1/2 duty when 1/2 duty is used, interconnect pins v 2 and v 3 as shown in figure 13.3. v cc v 1 v 2 v 3 v ss v 0 figure 13.3 handling of lcd drive power supply when using 1/2 duty b. large-panel display as the impedance of the built-in power supply split-resistance is large, it may not be suitable for driving a large panel. if the display lacks sharpness when using a large panel, refer to section 13.3.6, boosting the lcd drive power supply. when static or 1/2 duty is selected, the common output drive capability can be increased. set cmx to 1 when selecting the duty cycle. in this mode, with a static duty cycle pins com 4 to com 1 output the same waveform, and with 1/2 duty the com 1 waveform is output from pins com 2 and com 1 , and the com 2 waveform is output from pins com 4 and com 3 . c. luminance adjustment function (v 0 pin) connecting a resistance between the v 0 and v 1 pins enables the luminance to be adjusted. for details, see section 13.3.3, luminance adjustment function (v 0 pin). section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 410 of 626 rej09b0144-0600 d. lcd drive power supply setting with the h8/3827r group, there are two ways of providing lcd power: by using the on-chip power supply circuit, or by using an external circuit. when the on-chip power supply circuit is used for the lcd drive power supply, the v 0 and v 1 pins should be interconnected externally, as shown in figure 13.4 (a). when an external power supply circuit is used for the lcd drive power supply, connect the external power supply to the v 1 pin, and short the v 0 pin to v cc externally, as shown in figure 13.4 (b). v cc v 1 v 2 v 3 v ss v 0 (a) using on-chip power supply circuit v cc v 1 v 2 v 3 v ss v 0 (b) using external power supply circuit external power supply figure 13.4 examples of lcd power supply pin connections e. low-power-consumption lcd drive system use of a low-power-consumption lcd drive system enables the power consumption required for lcd drive to be optimized. for details, see section 13.3.4, low-power-consumption lcd drive system. f. segment external expansion the number of segments can be increased by connecting an hd66100 externally. for details, see section 13.3.7, connection to hd66100. section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 411 of 626 rej09b0144-0600 2. software settings a. duty selection any of four duty cycles?static, 1/2 duty, 1/3 duty, or 1/4 duty?can be selected with bits dts1 and dts0. b. segment selection the segment drivers to be used can be selected with bits sgs 3 to sgs 0 . c. frame frequency selection the frame frequency can be selected by setting bits cks 3 to cks 0 . the frame frequency should be selected in accordance with the lcd panel specification. for the clock selection method in watch mode, subactive mode, and subsleep mode, see section 13.3.5, operation in power-down modes. d. a or b waveform selection either the a or b waveform can be selected as the lcd waveform to be used by means of lcdab. section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 412 of 626 rej09b0144-0600 13.3.2 relationship between lcd ram and display the relationship between the lcd ram and the display segments differs according to the duty cycle. lcd ram maps for the different duty cycles when segment external expansion is not used are shown in figures 13.5 to 13.8, and lcd ram maps when segment external expansion is used in figures 13.9 to 13.12. after setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary ram, and display is started automatically when turned on. word- or byte-access instructions can be used for ram setting. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg 2 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 seg 1 seg 32 h'f740 h'f74f seg 32 seg 32 seg 32 seg 31 seg 31 seg 31 seg 31 com 4 com 3 com 2 com 1 com 4 com 3 com 2 com 1 figure 13.5 lcd ram map when not using segment external expansion (1/4 duty) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 413 of 626 rej09b0144-0600 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 h'f740 h'f74f seg 32 seg 32 seg 32 seg 31 seg 31 seg 31 com 3 com 2 com 1 com 3 com 2 com 1 space not used for display figure 13.6 lcd ram map when not using segment external expansion (1/3 duty) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 414 of 626 rej09b0144-0600 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg 4 seg 4 seg 3 seg 3 seg 2 seg 2 seg 1 seg 1 seg 32 h'f740 h'f747 h'f74f seg 32 seg 31 seg 31 seg 30 seg 30 seg 29 seg 29 com 2 com 1 com 2 com 1 com 2 com 1 com 2 com 1 display space space not used for display figure 13.7 lcd ram map when not using segment external expansion (1/2 duty) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 32 h'f740 h'f743 h'f74f seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 25 com 1 com 1 com 1 com 1 com 1 com 1 com 1 com 1 space not used for display display space figure 13.8 lcd ram map when not using segment external expansion (static mode) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 415 of 626 rej09b0144-0600 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg 2 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 seg 1 seg 64 h'f740 h'f75f seg 64 seg 64 seg 64 seg 63 seg 63 seg 63 seg 63 com 4 com 3 com 2 com 1 com 4 com 3 com 1 com 1 expansion driver display space figure 13.9 lcd ram map when using segment external expansion (sgx = ?1?, sgs3 to sgs0 = ?0000? 1/4 duty) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 416 of 626 rej09b0144-0600 space not used for display bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg 2 seg 2 seg 2 seg 1 seg 1 seg 1 h'f740 h'f75f seg 64 seg 64 seg 64 seg 63 seg 63 seg 63 com 3 com 2 com 1 com 3 com 1 com 1 expansion driver display space figure 13.10 lcd ram map when using segment external expansion (sgx = ?1?, sgs3 to sgs0 = ?0000? 1/3 duty) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 417 of 626 rej09b0144-0600 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg 4 seg 4 seg 3 seg 3 seg 2 seg 2 seg 1 seg 1 seg 128 h'f740 h'f75f seg 128 seg 127 seg 127 seg 126 seg 126 seg 125 seg 125 com 2 com 1 com 2 com 1 com 2 com 1 com 2 com 1 expansion driver display space figure 13.11 lcd ram map when using segment external expansion (sgx = ?1?, sgs3 to sgs0 = ?0000? 1/2 duty) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 418 of 626 rej09b0144-0600 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit0 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 256 h'f740 h'f75f seg 255 seg 254 seg 253 seg 252 seg 251 seg 250 seg 249 com 1 com 1 com 1 com 1 com 1 com 1 com 1 com 1 expansion driver display space figure 13.12 lcd ram map when using segment external expansion (sgx = ?1?, sgs3 to sgs0 = ?0000? static) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 419 of 626 rej09b0144-0600 13.3.3 luminance adjustment function (v 0 pin) figure 13.13 shows a detailed block diagram of the lcd drive power supply unit. the voltage output to the v 0 pin is v cc. when either of these voltages is used directly as the lcd drive power supply, the v 0 and v 1 pins should be shorted. also, connecting a variable resistance, r, between the v 0 and v 1 pins makes it possible to adjust the voltage applied to the v 1 pin, and so to provide luminance adjustment for the lcd panel. v cc v ss v 0 v 1 v 2 v 3 r figure 13.13 lcd drive power supply unit section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 420 of 626 rej09b0144-0600 13.3.4 low-power-consumption lcd drive system the use of the built-in split-resistance is normally the easiest method for implementing the lcd power supply circuit, but since the built-in resistance is fixed, a certain direct current flows constantly from the built-in resistance?s v cc to v ss . as this current does not depend on the current dissipation of the lcd panel, if an lcd panel with a small current dissipation is used, a wasteful amount of power will be consumed. the h8/3827 group is equipped with a function to minimize this waste of power. use of this function makes it possible to achieve the optimum power supply circuit for the lcd panel?s current dissipation. 1. principles a. capacitors are connected as external circuits to lcd power supply pins v1, v2, and v3, as shown in figure 13.14. b. the capacitors connected to v1, v2, and v3 are repeatedly charged and discharged in the cycle shown in figure 13.14, maintaining the potentials. c. at this time, the charged potential is a potential corresponding to the v1, v2, and v3 pins, respectively. (for example, with 1/3 bias drive, the charge for v2 is 2/3 that of v1, and that for v3 is 1/3 that of v1.) d. power is supplied to the lcd panel by means of the charges accumulated in these capacitors. e. the capacitances and charging/discharging periods of these capacitors are therefore determined by the current dissipation of the lcd panel. f. the charging and discharging periods can be selected by software. 2. example of operation (with 1/3 bias drive) a. during charging period tc in the figure, the potential is divided among pins v1, v2, and v3 by the built-in split-resistance (the potential of v2 being 2/3 that of v1, and that of v3 being 1/3 that of v1), as shown in figure 13.14, and external capacitors c1, c2, and c3 are charged. the lcd panel is continues to be driven during this time. b. in the following discharging period, tdc, charging is halted and the charge accumulated in each capacitor is discharged, driving the lcd panel. c. at this time, a slight voltage drop occurs due to the discharging; optimum values must be selected for the charging period and the capacitor capacitances to ensure that this does not affect the driving of the lcd panel. d. in this way, the capacitors connected to v1, v2, and v3 are repeatedly charged and discharged in the cycle shown in figure 13.14, maintaining the potentials and continuously driving the lcd panel. section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 421 of 626 rej09b0144-0600 e. as can be seen from the above description, the capacitances and charging/discharging periods of the capacitors are determined by the current dissipation of the lcd panel used. the charging/discharging periods can be selected with bits cds3 to cds0. f. the actual capacitor capacitances and charging/discharging periods must be determined experimentally in accordance with the current dissipation requirements of the lcd panel. an optimum current value can be selected, in contrast to the case in which a direct current flows constantly in the built-in split-resistance. v0 v1 v2 v3 c3 c2 c1 v1 potential v2 potential v3 potential charging period tc discharging period tdc vd1 vd2 vd3 voltage drop associated with discharging due to lcd panel driving v1 2/3 v1 1/3 power supply voltage fluctuation in 1/3 bias system figure 13.14 example of low-power-consumption lcd drive operation section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 422 of 626 rej09b0144-0600 1 frame m data com 1 com 2 com 3 com 4 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss (a) waveform with 1/4 duty 1 frame m data com 1 com 2 com 3 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss 1 frame m data com 1 com 2 seg n v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss 1 frame m data com 1 seg n v 1 v ss v 1 v ss (b) waveform with 1/3 duty (c) waveform with 1/2 duty (d) waveform with static output figure 13.15 output waveforms for each duty cycle (a waveform) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 423 of 626 rej09b0144-0600 m data com 1 com 2 seg n v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss m data com 1 seg n v 1 v ss v 1 v ss (c) waveform with 1/2 duty (d) waveform with static output 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame (b) waveform with 1/3 duty m data com 3 seg n com 1 v 1 v 2 v 3 v ss com 2 v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss (a) waveform with 1/4 duty m data com 1 com 2 com 3 com 4 seg n v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame v 1 v 2, v 3 v ss figure 13.16 output waveforms for each duty cycle (b waveform) section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 424 of 626 rej09b0144-0600 table 13.3 output levels data 0011 m 0101 static common output v 1 v ss v 1 v ss segment output v 1 v ss v ss v 1 1/2 duty common output v 2 , v 3 v 2 , v 3 v 1 v ss segment output v 1 v ss v ss v 1 1/3 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 1/4 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 13.3.5 operation in power-down modes in this lsi, the lcd controller/driver can be operated even in the power-down modes. the operating state of the lcd controller/driver in the power-down modes is summarized in table 13.4. in subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless w, w/2, or w/4 has been selected by bits cks3 to cks0, the clock will not be supplied and display will halt. since there is a possibility that a direct current will be applied to the lcd panel in this case, it is essential to ensure that w, w/2, or w/4 is selected. in active (medium-speed) mode, the system clock is switched, and therefore cks3 to cks0 must be modified to ensure that the frame frequency does not change. section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 425 of 626 rej09b0144-0600 table 13.4 power-down modes and display operation mode reset active sleep watch sub- active sub- sleep standby module standby clock runs runs runs stops stops stops stops stops * 4 w runs runs runs runs runs runs stops * 1 stops * 4 act = ?0? stops stops stops stops stops stops stops * 2 stops display operation act = ?1? stops functions functions functions * 3 functions * 3 functions * 3 stops * 2 stops notes: 1. the subclock oscillator does not stop, but clock supply is halted. 2. the lcd drive power supply is turned off regardless of the setting of the psw bit. 3. display operation is performed only if w, w/2, or w/4 is selected as the operating clock. 4. the clock supplied to the lcd stops. 13.3.6 boosting the lcd drive power supply when a large panel is driven, the on-chip power supply capacity may be insufficient. if the power supply capacity is insufficient when v cc is used as the power supply, the power supply impedance must be reduced. this can be done by connecting bypass capacitors of around 0.1 to 0.3 f to pins v 1 to v 3 , as shown in figure 13.17, or by adding a split-resistance externally. this lsi v cc v ss v 1 v 2 v 3 r r r r = several k ? to several m ? c = 0.1 to 0.3 f v 0 figure 13.17 connection of external split-resistance section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 426 of 626 rej09b0144-0600 13.3.7 connection to hd66100 if the segments are to be expanded externally, an hd66100 should be connected. connecting one hd66100 provides 80-segment expansion. when carrying out external expansion, select the external expansion signal function of pins seg 32 to seg 29 with the sgx bit in lpcr, and set bits sgs3 to sgs0 to 0000 or 0001. data is output externally from seg 1 of the lcd ram. seg 28 to seg 1 function as ports. figure 13.18 shows examples of connection to an hd66100. the output level is determined by a combination of the data and the m pin output, but these combinations differ from those in the hd66100. table 13.3 shows the output levels of the lcd drive power supply, and figures 13.15 and 13.16 show the common and segment waveforms for each duty cycle. when act is cleared to 0, operation stops with cl 2 = 0, cl 1 = 0, m = 0, and do at the data value (1 or 0) being output at that instant. in standby mode, the expansion pins go to the high- impedance (floating) state. when external expansion is implemented, the load in the lcd panel increases and the on-chip power supply may not provide sufficient current capacity. in this case, measures should be taken as described in section 13.3.6, boosting the lcd drive power supply. section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 427 of 626 rej09b0144-0600 v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 v cc v 0 v 1 v 2 v 3 v ss seg 32 /cl 1 seg 31 /cl 2 seg 30 /do seg 29 /m this lsi (a) 1/3 bias, 1/4 or 1/3 duty v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 v cc v 0 v 1 v 2 v 3 v ss seg 32 /cl 1 seg 31 /cl 2 seg 30 /do seg 29 /m this lsi (b) 1/2 duty v cc v 1 v 4 v 3 v 2 gnd v ee shl cl 1 cl 2 di m hd66100 v cc v 0 v 1 v 2 v 3 v ss seg 32 /cl 1 seg 31 /cl 2 seg 30 /do seg 29 /m this lsi (c) static mode figure 13.18 connection to hd66100 section 13 lcd controller/driver rev. 6.00 aug 04, 2006 page 428 of 626 rej09b0144-0600 section 14 power supply circuit rev. 6.00 aug 04, 2006 page 429 of 626 rej09b0144-0600 section 14 power supply circuit 14.1 overview h8/3827r group, h8/38327 group and h8/38427 group incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v to 3.2 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 3.0 v or above can be held down to virtually the same low level as when used at approximately 3.0 v. if the external power supply is 3.0 v or below, the internal voltage will be practically the same as the external voltage. it is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step- down circuit. 14.2 when using internal power supply step-down circuit connect the external power supply to the v cc pin, and connect a capacitance of approximately 0.1 f, in the case of the h8/3827r, or approximately 0.33 f, in the case of the h8/38327 or h8/38427, between cv cc and v ss , as shown in figure 14.1. the internal step-down circuit is made effective simply by adding this external circuit. in the external circuit interface, the external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. the lcd power supply and a/d converter analog power supply are not affected by the internal step-down current. in the h8/3827r group the operating range differs depending on whether or not the internal step- down circuit is used. for details, see section 15, electrical characteristics. cv cc v ss internal logic step-down circuit internal power supply stabilization capacitance (approximately 0.1 f, in the case of the h8/3827r, or approximately 0.33 f, in the case of the h8/38327 or h8/38427) v cc figure 14.1 power supply connection when internal step-down circuit is used section 14 power supply circuit rev. 6.00 aug 04, 2006 page 430 of 626 rej09b0144-0600 14.3 when not using internal power supply step-down circuit when the internal power supply step-down circuit is not used, connect the external power supply to the cv cc pin and v cc pin, as shown in figure 14.2. the external power supply is then input directly to the internal power supply. the permissible range for the power supply voltage is 1.8 v to 5.5 v for the h8/3827r group and 2.7 v to 3.6 v for the h8/38327 group and h8/38427 group. normally, however, the internal power supply step-down circuit should be used. operation cannot be guaranteed if a voltage outside this range is input. cv cc v ss internal logic step-down circuit internal power supply v cc figure 14.2 power supply connection when internal step-down circuit is not used 14.4 h8/3827s group the h8/3827s group has two v cc pins, which should be interconnected externally. 14.5 notes on switching from the h8/3827r to the h8/38327 or h8/38427 examine the following with regard to the power supply circuit. (1) if the internal power supply step-down circuit was used on the h8/3827r the stabilization capacitance value differs between the products. it is necessary to change the value from 0.1 f (h8/3827r) to 0.33 f (h8/38327 or h8/38427). note that these values are rough guidelines and it is still necessary to confirm system operation. (2) if the internal power supply step-down circuit was not used on the h8/3827r use of the internal power supply step-down circuit of the h8/38327 or h8/38427 is recommended. furthermore, operation at a v cc of 3.6 v or greater is not guaranteed if the internal power supply step-down circuit is not used. it is therefore necessary to change the cv cc connection to use the internal power supply step-down circuit. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 431 of 626 rej09b0144-0600 section 15 electrical characteristics 15.1 h8/3827r group absolute maximum ratings (regular specifications) table 15.1 lists the absolute maximum ratings. table 15.1 absolute maximum ratings item symbol value unit notes power supply voltage v cc , cv cc ?0.3 to +7.0 v * 1 analog power supply voltage av cc ?0.3 to +7.0 v programming voltage v pp ?0.3 to +13.0 v input voltage ports other than port b v in ?0.3 to v cc +0.3 v port b av in ?0.3 to av cc +0.3 v operating temperature t opr ?20 to +75 * 2 c storage temperature t stg ?55 to +125 c notes: 1. permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 2. the operating temperature is the temperature range in which power (voltage v cc shown in "electrical characteristics") can be applied to the chip. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 432 of 626 rej09b0144-0600 15.2 h8/3827r group electrical characteristics (regular specifications) 15.2.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 1. power supply voltage and oscillator frequency range 38.4 1.8 3.0 5.5 v cc (v) f w (khz) all operating modes 32.768 4.5 16.0 4.0 10.0 2.0 1.8 2.7 4.5 5.5 v cc (v) v cc (v) fosc (mhz) fosc (mhz) active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit not used 4.0 10.0 2.0 1.8 2.7 5.5 active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit used note: fosc is the oscillator frequency. when external clocks are used, fosc=1mhz is the minimum. note: fosc is the oscillator frequency. when external clocks are used, fosc=1mhz is the minimum. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 433 of 626 rej09b0144-0600 2. power supply voltage and operating frequency range 16.384 8.192 4.096 1.8 3.6 5.5 v cc (v) sub (khz) 19.2 9.6 4.8 8.0 2.0 5.0 (0.5) 1.0 1.8 2.7 4.5 5.5 v cc (v) v cc (v) (mhz) (mhz) 1000 250 625 (7.813) 15.625 1.8 2.7 4.5 5.5 v cc (v) (khz) 2.0 5.0 (0.5) 1.0 1.8 2.7 5.5 v cc (v) (khz) 250 625 (7.813) 15.625 1.8 2.7 5.5 active (medium-speed) mode (except a/d converter) sleep (medium-speed) mode (except a/d converter) internal power supply step-down circuit not used active (high-speed) mode sleep (high-speed) mode (except cpu) internal power supply step-down circuit not used active (high-speed) mode sleep (high-speed) mode (except cpu) internal power supply step-down circuit used active (medium-speed) mode (except a/d converter) sleep (medium-speed) mode (except a/d converter) internal power supply step-down circuit used subactive mode subsleep mode (except cpu) watch mode (except cpu) figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =1mhz. note: figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =1mhz. note: figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =15.625khz. note: figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =15.625khz. note: section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 434 of 626 rej09b0144-0600 3. analog power supply voltage and a/d converter operating range 625 1000 500 1.8 2.7 5.5 av cc (v) (khz) 5.0 1.0 0.5 1.8 2.7 4.5 5.5 av cc (v) (mhz) 4.5 625 500 1.8 2.7 5.5 av cc (v) (khz) 4.5 active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit not used and used active (medium-speed) mode sleep (medium-speed) mode internal power supply step-down circuit not used active (medium-speed) mode sleep (medium-speed) mode internal power supply step-down circuit used section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 435 of 626 rej09b0144-0600 15.2.2 dc characteristics table 15.2 lists the dc characteristics. table 15.2 dc characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?20c to +75c * 4 (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes v ih 0.8 v cc ?v cc + 0.3 v v cc = 4.0 v to 5.5 v input high voltage res , wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig sck 31 , sck 32 , adtrg 0.9 v cc ?v cc + 0.3 except the above 0.7 v cc ?v cc + 0.3 v v cc = 4.0 v to 5.5 v rxd 31 , rxd 32 , ud 0.8 v cc ?v cc + 0.3 except the above osc 1 0.8 v cc ?v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.9 v cc ?v cc + 0.3 except the above x 1 0.9 v cc ?v cc + 0.3 v v cc = 1.8 v to 5.5 v 0.7 v cc ?v cc + 0.3 v v cc = 4.0 v to 5.5 v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.8 v cc ?v cc + 0.3 except the above pb 0 to pb 7 0.7 v cc ?av cc + 0.3 v cc = 4.0 v to 5.5 v 0.8 v cc ?av cc + 0.3 except the above note: connect the test pin to v ss . section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 436 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes v il ?0.3 ? 0.2 v cc vv cc = 4.0 v to 5.5 v input low voltage res , wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig sck 31 , sck 32 , adtrg ?0.3 ? 0.1 v cc except the above ?0.3 ? 0.3 v cc vv cc = 4.0 v to 5.5 v rxd 31 , rxd 32 , ud ?0.3 ? 0.2 v cc except the above osc 1 ?0.3 ? 0.2 when internal step- down circuit is used. ?0.3 ? 0.2 v cc vv cc = 4.0 v to 5.5 v ?0.3 ? 0.1 v cc except the above x 1 ?0.3 ? 0.1 v cc vv cc = 1.8 v to 5.5 v ?0.3 ? 0.3 v cc vv cc = 4.0 v to 5.5 v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 , pb 0 to pb 7 ?0.3 ? 0.2 v cc except the above output high voltage v oh v cc ? 1.0 ? ? v v cc = 4.0 v to 5.5 v ?i oh = 1.0 ma v cc ? 0.5 ? ? v cc = 4.0 v to 5.5 v ?i oh = 0.5 ma p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc ? 0.3 ? ? ?i oh = 0.1 ma section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 437 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes output low voltage v ol p1 0 to p1 7 , p4 0 to p4 2 ??0.6 vv cc = 4.0 v to 5.5 v i ol = 1.6 ma ??0.5 i ol = 0.4 ma p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 ??0.5 i ol = 0.4 ma p3 0 to p3 7 ??1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma ??0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma ??0.5 i ol = 0.4 ma | i il | res , p4 3 ? ? 20.0 a * 2 ??1.0 v in = 0.5 v to v cc ? 0.5 v * 1 input/output leakage current osc 1 , x 1 , p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 ??1.0 av in = 0.5 v to v cc ? 0.5 v pb 0 to pb 7 ??1.0 v in = 0.5 v to av cc ? 0.5 v ?i p 50.0 ? 300.0 a v cc = 5 v, v in = 0 v pull-up mos current p1 0 to p1 7 , p3 0 to p3 7 , p5 0 to p5 7 , p6 0 to p6 7 ? 35.0 ? v cc = 2.7 v, v in = 0 v reference value section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 438 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes input capacitance c in all input pins except power supply, res , p4 3 , pb 0 to pb 7 ? ? 15.0 pf f = 1mhz, v in =0 v, t a = 25c res ? ? 80.0 * 2 ? ? 15.0 * 1 p4 3 ? ? 50.0 * 2 ? ? 15.0 * 1 pb 0 to pb 7 ? ? 15.0 i ope1 v cc ? 4.5 6.5 ma active (high-speed) mode v cc = 5 v, f osc = 10mhz * 3 * 5 * 6 active mode current dissipation i ope2 v cc ? 1.3 2.0 ma active (medium- speed) mode v cc = 5 v, f osc = 10mhz divided by 128 * 3 * 5 * 6 sleep mode current dissipation i sleep v cc ?2.54.0 mav cc =5 v, f osc =10mhz * 3 * 5 * 6 subactive mode current dissipation i sub v cc ?1530 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 5 * 6 ?8? av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /8) * 3 * 5 reference value * 6 subsleep mode current dissipation i subsp v cc ?7.516 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 5 * 6 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 439 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes watch mode current dissipation i watch v cc ?2.86 av cc = 2.7 v, 3 2 khz crystal oscillator lcd not used * 3 * 5 * 6 standby mode current dissipation i stby v cc ? 1.0 5.0 a 32 khz crystal oscillator not used * 3 * 5 ram data retaining voltage v ram v cc 1.5 ? ? v * 3 * 5 i ol output pins except port 3 ??2.0 mav cc = 4.0 v to 5.5 v port 3 ? ? 10.0 v cc = 4.0 v to 5.5 v allowable output low current (per pin) all output pins ? ? 0.5 i ol output pins except port 3 ? ? 40.0 ma v cc = 4.0 v to 5.5 v port 3 ? ? 80.0 v cc = 4.0 v to 5.5 v allowable output low current (total) all output pins ? ? 20.0 ?i oh all output pins ? ? 2.0 ma v cc = 4.0 v to 5.5 v allowable output high current (per pin) ? ? 0.2 except the above ? i oh all output pins ? ? 15.0 ma v cc = 4.0 v to 5.5 v allowable output high current (total) ? ? 10.0 except the above notes: 1. applies to the mask rom products. 2. applies to the hd6473827r. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 440 of 626 rej09b0144-0600 3. pin states during current measurement. mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) v cc only cpu operates v cc halted active (medium- speed) mode (i ope2 ) sleep mode v cc only timers operate v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd subactive mode v cc only cpu operates v cc halted subsleep mode v cc only timers operate, cpu stops v cc halted watch mode v cc only time base operates, cpu stops v cc halted system clock oscillator: crystal subclock oscillator: crystal standby mode v cc cpu and timers both stop v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd 4. the guaranteed temperature as an electrical characteristic for die products is 75 c. 5. excludes current in pull-up mos transistors and output buffers. 6. when internal step-down circuit is used. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 441 of 626 rej09b0144-0600 15.2.3 ac characteristics table 15.3 lists the control signal timing, and tables 15.4 lists the serial interface timing. table 15.3 control signal timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?20c to +75c * 4 (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition reference figure f osc osc 1 , osc 2 2? 16 mhzv cc = 4.5 v to 5.5 v * 2 2? 10 v cc = 2.7 v to 5.5 v system clock oscillation frequency 2? 4 v cc = 1.8 v to 5.5 v osc clock ( osc ) cycle time t osc osc 1 , osc 2 62.5 ? 500 (1000) ns v cc = 4.5 v to 5.5 v figure 15.1 * 2 * 3 100 ? 500 (1000) v cc = 2.7 v to 5.5 v figure 15.1 250 ? 500 (1000) v cc = 1.8 v to 5.5 v * 3 t cyc 2 ? 128 t osc system clock ( ) cycle time ? ? 244.1 s subclock oscillation frequency f w x 1 , x 2 ? 32.768 or 38.4 ?khz watch clock ( w ) cycle time t w x 1 , x 2 ? 30.5 or 26.0 ? s figure 15.1 subclock ( sub ) cycle time t subcyc 2? 8 t w * 1 instruction cycle time 2? ? t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 ? 20 45 s figure 15.9 v cc = 2.2 v to 5.5 v figure 15.9 * 2 ? 0.1 8 ms figure 15.9 v cc = 2.2 v to 5.5 v figure 15.9 ? ? 50 ms except the above section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 442 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition reference figure oscillation stabilization time t rc x 1 , x 2 ?? 2.0s t cph osc 1 25 ? ? ns v cc = 4.5 v to 5.5 v external clock high width figure 15.1 * 2 40 ? ? v cc = 2.7 v to 5.5 v figure 15.1 100 ? ? v cc = 1.8 v to 5.5 v x 1 ? 15.26 or 13.02 ?s t cpl osc 1 25 ? ? ns v cc = 4.5 v to 5.5 v external clock low width figure 15.1 * 2 40 ? ? v cc = 2.7 v to 5.5 v figure 15.1 100 ? ? v cc = 1.8 v to 5.5 v x 1 ? 15.26 or 13.02 ?s t cpr osc 1 ?? 6 ns v cc = 4.5 v to 5.5 v external clock rise time figure 15.1 * 2 ?? 10 v cc = 2.7 v to 5.5 v figure 15.1 ?? 25 v cc = 1.8 v to 5.5 v x 1 ? ? 55.0 ns t cpf osc 1 ?? 6 ns v cc = 4.5 v to 5.5 v external clock fall time figure 15.1 * 2 ?? 10 v cc = 2.7 v to 5.5 v figure 15.1 ?? 25 v cc = 1.8 v to 5.5 v x 1 ? ? 55.0 ns pin res low width t rel res 10 ? ? t cyc figure 15.2 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 443 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition reference figure input pin high width t ih irq 0 to irq 4 , wkp 0 to wkp 7 adtrg , tmic tmif, tmig, aevl, aevh 2? ?t cyc t subcyc figure 15.3 input pin low width t il irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmic, tmif, tmig, aevl, aevh 2? ?t cyc t subcyc figure 15.3 ud pin minimum modulation width t udh t udl ud 4 ? ? t cyc t subcyc figure 15.4 notes: 1. selected with sa1 and sa0 of system clock control register 2 (syscr2). 2. internal power supply step-down circuit not used 3. figures in parentheses are the maximum t osc rate with external clock input. 4. the guaranteed temperature as an electrical characteristic for die products is 75 c. table 15.4 serial interface (sci3-1, sci3-2) timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?20c to +75c * 2 (including subactive mode) unless otherwise indicated. values item symbol min typ max unit test conditions reference figure asynchronous t scyc 4 ? ? figure 15.5 input clock cycle synchronous 6 ? ? t cyc or t subcyc input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 15.5 t txd ??1 v cc = 4.0 v to 5.5 v figure 15.6 transmit data delay time (synchronous) ??1 t cyc or t subcyc except the above t rxs 200.0 ? ? ns v cc = 4.0 v to 5.5 v figure 15.6 * 1 receive data setup time (synchronous) 400.0 ? ? except the above figure 15.6 t rxh 200.0 ? ? ns v cc = 4.0 v to 5.5 v figure 15.6 * 1 receive data hold time (synchronous) 400.0 ? ? except the above figure 15.6 notes: 1. when internal step-down circuit is not used. 2. the guaranteed temperature as an electrical characteristic for die products is 75 c. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 444 of 626 rej09b0144-0600 15.2.4 a/d converter characteristics table 15.5 shows the a/d converter characteristics. table 15.5 a/d converter characteristics v cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?20c to +75c * 6 (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes analog power supply voltage av cc av cc 1.8 ? 5.5 v * 1 analog input voltage av in an 0 to an 7 ? 0.3 ? av cc + 0.3 v ai ope av cc ??1.5 maav cc = 5 v analog power supply current ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ??5 a * 3 analog input capacitance c ain an 0 to an 7 ? ? 15.0 pf allowable signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bit nonlinearity error ??2.5 lsbav cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v * 4 ??5.5 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v ? ? 7.5 except the above * 5 quantization error ??0.5 lsb section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 445 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes absolute accuracy ??3.0 lsbav cc = 3.0 v to 5.5 v v cc = 3.0 v to 5.5 v * 4 ??6.0 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v ? ? 8.0 except the above * 5 conversion time 12.4 ? 124 s av cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v * 4 62 ? 124 except the above notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 4. when internal step-down circuit is not used. 5. conversion time 62 s 6. the guaranteed temperature as an electrical characteristic for die products is 75 c. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 446 of 626 rej09b0144-0600 15.2.5 lcd characteristics table 15.6 shows the lcd characteristics. table 15.6 lcd characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?20c to +75c * 3 (including subactive mode) unless otherwise specified. test values item symbol applicable pins conditions min typ max unit notes segment driver drop voltage v ds seg 1 to seg 32 i d = 2 a v 1 = 2.7 to 5.5 v ??0.6v * 1 common driver drop voltage v dc com 1 to com 4 i d = 2 a v 1 = 2.7 to 5.5 v ??0.3v * 1 lcd power supply split-resistance r lcd between v 1 and v ss 0.5 3.0 9.0 m ? liquid crystal display voltage v lcd v 1 2.2 ? 5.5 v * 2 notes: 1. the voltage drop from power supply pins v 1 , v 2 , v 3 , and v ss to each segment pin or common pin. 2. when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v 1 v 2 v 3 v ss . 3. the guaranteed temperature as an electrical characteristic for die products is 75 c. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 447 of 626 rej09b0144-0600 table 15.7 ac characteristics for external segment expansion v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c * 2 (including subactive mode) unless otherwise specified. test values item symbol applicable pins conditions min typ max unit reference figure clock high width t cwh cl 1 , cl 2 * 1 800 ? ? ns figure 15.7 clock low width t cwl cl 2 * 1 800 ? ? ns figure 15.7 clock setup time t csu cl 1 , cl 2 * 1 500 ? ? ns figure 15.7 data setup time t su do * 1 300 ? ? ns figure 15.7 data hold time t dh do * 1 300 ? ? ns figure 15.7 m delay time t dm m * 1 ?1000 ? 1000 ns figure 15.7 clock rise and fall times t ct cl 1 , cl 2 ? ? 170 ns figure 15.7 notes: 1. value when the frame frequency is set to between 30.5 hz and 488 hz. 2. the guaranteed temperature as an electrical characteristic for die products is 75 c. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 448 of 626 rej09b0144-0600 15.3 h8/3827r group absolute maximum ratings (wide-range specification) table 15.8 lists the absolute maximum ratings. table 15.8 absolute maximum ratings item symbol value unit power supply voltage v cc , cv cc ?0.3 to +7.0 v analog power supply voltage av cc ?0.3 to +7.0 v programming voltage v pp ?0.3 to +13.0 v input voltage ports other than port b v in ?0.3 to v cc +0.3 v port b av in ?0.3 to av cc +0.3 v operating temperature t opr ?40 to +85 c storage temperature t stg ?55 to +125 c note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 449 of 626 rej09b0144-0600 15.4 h8/3827r group electrical characteristics (wide-range specification) 15.4.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 1. power supply voltage and oscillator frequency range 38.4 1.8 3.0 5.5 v cc (v) f w (khz) all operating modes 32.768 4.5 16.0 4.0 10.0 2.0 1.8 2.7 4.5 5.5 v cc (v) v cc (v) fosc (mhz) fosc (mhz) active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit not used 4.0 10.0 2.0 1.8 2.7 5.5 active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit used note: fosc is the oscillator frequency. when external clocks are used, fosc=1mhz is the minimum. note: fosc is the oscillator frequency. when external clocks are used, fosc=1mhz is the minimum. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 450 of 626 rej09b0144-0600 2. power supply voltage and operating frequency range 16.384 8.192 4.096 1.8 3.6 5.5 v cc (v) sub (khz) 19.2 9.6 4.8 8.0 2.0 5.0 (0.5) 1.0 1.8 2.7 4.5 5.5 v cc (v) v cc (v) (mhz) (mhz) 1000 250 625 (7.813) 15.625 1.8 2.7 4.5 5.5 v cc (v) (khz) 2.0 5.0 (0.5) 1.0 1.8 2.7 5.5 v cc (v) (khz) 250 625 (7.813) 15.625 1.8 2.7 5.5 active (medium-speed) mode (except a/d converter) sleep (medium-speed) mode (except a/d converter) internal power supply step-down circuit not used active (high-speed) mode sleep (high-speed) mode (except cpu) internal power supply step-down circuit not used active (high-speed) mode sleep (high-speed) mode (except cpu) internal power supply step-down circuit used active (medium-speed) mode (except a/d converter) sleep (medium-speed) mode (except a/d converter) internal power supply step-down circuit used subactive mode subsleep mode (except cpu) watch mode (except cpu) figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =1mhz. note: figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =1mhz. note: figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =15.625khz. note: figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =15.625khz. note: section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 451 of 626 rej09b0144-0600 3. analog power supply voltage and a/d converter operating range 625 1000 500 1.8 2.7 5.5 av cc (v) (khz) 5.0 1.0 0.5 1.8 2.7 4.5 5.5 av cc (v) (mhz) 4.5 625 500 1.8 2.7 5.5 av cc (v) (khz) 4.5 active (high-speed) mode sleep (high-speed) mode internal power supply step-down circuit not used and used active (medium-speed) mode sleep (medium-speed) mode internal power supply step-down circuit not used active (medium-speed) mode sleep (medium-speed) mode internal power supply step-down circuit used section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 452 of 626 rej09b0144-0600 15.4.2 dc characteristics table 15.9 lists the dc characteristics. table 15.9 dc characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?40c to +85c (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes v ih 0.8 v cc ?v cc + 0.3 v v cc = 4.0 v to 5.5 v input high voltage res , wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig sck 31 , sck 32 , adtrg 0.9 v cc ?v cc + 0.3 except the above 0.7 v cc ?v cc + 0.3 v v cc = 4.0 v to 5.5 v rxd 31 , rxd 32 , ud 0.8 v cc ?v cc + 0.3 except the above osc 1 0.8 v cc ?v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.9 v cc ?v cc + 0.3 except the above x 1 0.9 v cc ?v cc + 0.3 v v cc = 1.8 v to 5.5 v 0.7 v cc ?v cc + 0.3 v v cc = 4.0 v to 5.5 v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.8 v cc ?v cc + 0.3 except the above pb 0 to pb 7 0.7 v cc ?av cc + 0.3 v cc = 4.0 v to 5.5 v 0.8 v cc ?av cc + 0.3 except the above note: connect the test pin to v ss . section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 453 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes v il ?0.3 ? 0.2 v cc vv cc = 4.0 v to 5.5 v input low voltage res , wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig sck 31 , sck 32 , adtrg ?0.3 ? 0.1 v cc except the above ?0.3 ? 0.3 v cc vv cc = 4.0 v to 5.5 v rxd 31 , rxd 32 , ud ?0.3 ? 0.2 v cc except the above osc 1 ?0.3 ? 0.2 when internal step- down circuit is used. ?0.3 ? 0.2 v cc vv cc = 4.0 v to 5.5 v ?0.3 ? 0.1 v cc except the above x 1 ?0.3 ? 0.1 v cc vv cc = 1.8 v to 5.5 v ?0.3 ? 0.3 v cc vv cc = 4.0 v to 5.5 v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 , pb 0 to pb 7 ?0.3 ? 0.2 v cc except the above output high voltage v oh v cc ? 1.0 ? ? v v cc = 4.0 v to 5.5 v ?i oh = 1.0 ma v cc ? 0.5 ? ? v cc = 4.0 v to 5.5 v ?i oh = 0.5 ma p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc ? 0.3 ? ? ?i oh = 0.1 ma section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 454 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes output low voltage v ol p1 0 to p1 7 , p4 0 to p4 2 ??0.6 vv cc = 4.0 v to 5.5 v i ol = 1.6 ma ??0.5 i ol = 0.4 ma p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 ??0.5 i ol = 0.4 ma p3 0 to p3 7 ??1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma ??0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma ??0.5 i ol = 0.4 ma | i il | res , p4 3 ? ? 20.0 a * 2 ??1.0 v in = 0.5 v to v cc ? 0.5 v * 1 input/output leakage current osc 1 , x 1 , p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 ??1.0 av in = 0.5 v to v cc ? 0.5 v pb 0 to pb 7 ??1.0 v in = 0.5 v to av cc ? 0.5 v ?i p 50.0 ? 300.0 a v cc = 5 v, v in = 0 v pull-up mos current p1 0 to p1 7 , p3 0 to p3 7 , p5 0 to p5 7 , p6 0 to p6 7 ? 35.0 ? v cc = 2.7 v, v in = 0 v reference value section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 455 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes input capacitance c in all input pins except power supply, res , p4 3 , pb 0 to pb 7 ? ? 15.0 pf f = 1mhz, v in =0 v, t a = 25c res ? ? 80.0 * 2 ? ? 15.0 * 1 p4 3 ? ? 50.0 * 2 ? ? 15.0 * 1 pb 0 to pb 7 ? ? 15.0 i ope1 v cc ? 4.5 6.5 ma active (high-speed) mode v cc = 5 v, f osc = 10mhz * 3 * 4 * 5 active mode current dissipation i ope2 v cc ? 1.3 2.0 ma active (medium- speed) mode v cc = 5 v, f osc = 10mhz divided by 128 * 3 * 4 * 5 sleep mode current dissipation i sleep v cc ?2.54.0 mav cc =5 v, f osc =10mhz * 3 * 4 * 5 subactive mode current dissipation i sub v cc ?1530 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 4 * 5 ?8? av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /8) * 3 * 4 reference value * 5 subsleep mode current dissipation i subsp v cc ?7.516 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 4 * 5 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 456 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes watch mode current dissipation i watch v cc ?2.86 av cc = 2.7 v 3 2 khz crystal oscillator lcd not used * 3 * 4 * 5 standby mode current dissipation i stby v cc ? 1.0 5.0 a 32 khz crystal oscillator not used * 3 * 4 ram data retaining voltage v ram v cc 1.5 ? ? v * 3 * 4 i ol output pins except port 3 ??2.0 mav cc = 4.0 v to 5.5 v port 3 ? ? 10.0 v cc = 4.0 v to 5.5 v allowable output low current (per pin) all output pins ? ? 0.5 i ol output pins except port 3 ? ? 40.0 ma v cc = 4.0 v to 5.5 v port 3 ? ? 80.0 v cc = 4.0 v to 5.5 v allowable output low current (total) all output pins ? ? 20.0 ?i oh all output pins ? ? 2.0 ma v cc = 4.0 v to 5.5 v allowable output high current (per pin) ? ? 0.2 except the above ? i oh all output pins ? ? 15.0 ma v cc = 4.0 v to 5.5 v allowable output high current (total) ? ? 10.0 except the above notes: 1. applies to the mask rom products. 2. applies to the hd6473827r. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 457 of 626 rej09b0144-0600 3. pin states during current measurement. mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) v cc only cpu operates v cc halted active (medium- speed) mode (i ope2 ) sleep mode v cc only timers operate v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd subactive mode v cc only cpu operates v cc halted subsleep mode v cc only timers operate, cpu stops v cc halted watch mode v cc only time base operates, cpu stops v cc halted system clock oscillator: crystal subclock oscillator: crystal standby mode v cc cpu and timers both stop v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd 4. excludes current in pull-up mos transistors and output buffers. 5. when internal step-down circuit is used. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 458 of 626 rej09b0144-0600 15.4.3 ac characteristics table 15.10 lists the control signal timing, and tables 15.11 lists the serial interface timing. table 15.10 control signal timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?40c to +85c (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition reference figure f osc osc 1 , osc 2 2? 16 mhzv cc = 4.5 v to 5.5 v * 2 2? 10 v cc = 2.7 v to 5.5 v system clock oscillation frequency 2? 4 v cc = 1.8 v to 5.5 v osc clock ( osc ) cycle time t osc osc 1 , osc 2 62.5 ? 500 (1000) ns v cc = 4.5 v to 5.5 v figure 15.1 * 2 * 3 100 ? 500 (1000) v cc = 2.7 v to 5.5 v figure 15.1 250 ? 500 (1000) v cc = 1.8 v to 5.5 v * 3 t cyc 2 ? 128 t osc system clock ( ) cycle time ? ? 244.1 s subclock oscillation frequency f w x 1 , x 2 ? 32.768 or 38.4 ?khz watch clock ( w ) cycle time t w x 1 , x 2 ? 30.5 or 26.0 ? s figure 15.1 subclock ( sub ) cycle time t subcyc 2? 8 t w * 1 instruction cycle time 2? ? t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 ? 20 45 s figure 15.9 v cc = 2.2 v to 5.5 v figure 15.9 * 2 ? 0.1 8 ms figure 15.9 v cc = 2.2 v to 5.5 v figure 15.9 ? ? 50 ms except the above section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 459 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition reference figure oscillation stabilization time t rc x 1 , x 2 ?? 2.0s t cph osc 1 25 ? ? ns v cc = 4.5 v to 5.5 v external clock high width figure 15.1 * 2 40 ? ? v cc = 2.7 v to 5.5 v figure 15.1 100 ? ? v cc = 1.8 v to 5.5 v x 1 ? 15.26 or 13.02 ?s t cpl osc 1 25 ? ? ns v cc = 4.5 v to 5.5 v external clock low width figure 15.1 * 2 40 ? ? v cc = 2.7 v to 5.5 v figure 15.1 100 ? ? v cc = 1.8 v to 5.5 v x 1 ? 15.26 or 13.02 ?s t cpr osc 1 ?? 6 ns v cc = 4.5 v to 5.5 v external clock rise time figure 15.1 * 2 ?? 10 v cc = 2.7 v to 5.5 v figure 15.1 ?? 25 v cc = 1.8 v to 5.5 v x 1 ? ? 55.0 ns t cpf osc 1 ?? 6 ns v cc = 4.5 v to 5.5 v external clock fall time figure 15.1 * 2 ?? 10 v cc = 2.7 v to 5.5 v figure 15.1 ?? 25 v cc = 1.8 v to 5.5 v x 1 ? ? 55.0 ns pin res low width t rel res 10 ? ? t cyc figure 15.2 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 460 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition reference figure input pin high width t ih irq 0 to irq 4 , wkp 0 to wkp 7 adtrg , tmic tmif, tmig, aevl, aevh 2? ?t cyc t subcyc figure 15.3 input pin low width t il irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmic, tmif, tmig, aevl, aevh 2? ?t cyc t subcyc figure 15.3 ud pin minimum modulation width t udh t udl ud 4 ? ? t cyc t subcyc figure 15.4 notes: 1. selected with sa1 and sa0 of system clock control register 2 (syscr2). 2. internal power supply step-down circuit not used 3. figures in parentheses are the maximum t osc rate with external clock input. table 15.11 serial interface (sci3-1, sci3-2) timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?40c to +85c unless otherwise indicated. values item symbol min typ max unit test conditions reference figure asynchronous t scyc 4 ? ? figure 15.5 input clock cycle synchronous 6 ? ? t cyc or t subcyc input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 15.5 t txd ??1 v cc = 4.0 v to 5.5 v figure 15.6 transmit data delay time (synchronous) ??1 t cyc or t subcyc except the above t rxs 200.0 ? ? ns v cc = 4.0 v to 5.5 v figure 15.6 * receive data setup time (synchronous) 400.0 ? ? except the above figure 15.6 t rxh 200.0 ? ? ns v cc = 4.0 v to 5.5 v figure 15.6 * receive data hold time (synchronous) 400.0 ? ? except the above figure 15.6 note: * when internal step-down circuit is not used. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 461 of 626 rej09b0144-0600 15.4.4 a/d converter characteristics table 15.12 shows the a/d converter characteristics of the h8/3827r. table 15.12 a/d converter characteristics v cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?40c to +85c unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes analog power supply voltage av cc av cc 1.8 ? 5.5 v * 1 analog input voltage av in an 0 to an 7 ? 0.3 ? av cc + 0.3 v ai ope av cc ??1.5 maav cc = 5 v analog power supply current ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ??5 a * 3 analog input capacitance c ain an 0 to an 7 ? ? 15.0 pf allowable signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bit nonlinearity error ??2.5 lsbav cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v * 4 ??5.5 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v ? ? 7.5 except the above * 5 quantization error ??0.5 lsb section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 462 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes absolute accuracy ??3.0 lsbav cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v * 4 ??6.0 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v ? ? 8.0 except the above * 5 conversion time 12.4 ? 124 s av cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v * 4 62 ? 124 except the above notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 4. when internal step-down circuit is not used. 5. conversion time 62 s section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 463 of 626 rej09b0144-0600 15.4.5 lcd characteristics table 15.13 shows the lcd characteristics. table 15.13 lcd characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?40c to +85c (including subactive mode) unless otherwise specified. values item symbol applicable pins test conditions min typ max unit notes segment driver drop voltage v ds seg 1 to seg 32 i d = 2 a v 1 = 2.7 to 5.5 v ??0.6v * 1 common driver drop voltage v dc com 1 to com 4 i d = 2 a v 1 = 2.7 to 5.5 v ??0.3v * 1 lcd power supply split-resistance r lcd between v 1 and v ss 0.5 3.0 9.0 m ? liquid crystal display voltage v lcd v 1 2.2 ? 5.5 v * 2 notes: 1. the voltage drop from power supply pins v 1 , v 2 , v 3 , and v ss to each segment pin or common pin. 2. when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v 1 v 2 v 3 v ss . section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 464 of 626 rej09b0144-0600 table 15.14 ac characteristics for external segment expansion v cc = 1.8 v to 5.5 v, v ss = 0.0 v, t a = ?40c to +85c (including subactive mode) unless otherwise specified. test values item symbol applicable pins conditions min typ max unit reference figure clock high width t cwh cl 1 , cl 2 * 800 ? ? ns figure 15.7 clock low width t cwl cl 2 * 800 ? ? ns figure 15.7 clock setup time t csu cl 1 , cl 2 * 500 ? ? ns figure 15.7 data setup time t su do * 300 ? ? ns figure 15.7 data hold time t dh do * 300 ? ? ns figure 15.7 m delay time t dm m * ?1000 ? 1000 ns figure 15.7 clock rise and fall times t ct cl 1 , cl 2 ? ? 170 ns figure 15.7 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 465 of 626 rej09b0144-0600 15.5 h8/3827s group absolute maximum ratings table 15.15 lists the absolute maximum ratings. table 15.15 absolute maximum ratings item symbol value unit notes power supply voltage v cc ?0.3 to +4.3 v * 1 analog power supply voltage av cc ?0.3 to +4.3 v input voltage ports other than port b v in ?0.3 to v cc +0.3 v port b av in ?0.3 to av cc +0.3 v operating temperature t opr ?20 to +75 (regular specifications) c ?40 to +85 (wide-range specifications) +75 (products shipped as chips) * 2 storage temperature t stg ?55 to +125 c notes: 1. permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 2. power may be applied when the temperature is between ?20 and ?75c. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 466 of 626 rej09b0144-0600 15.6 h8/3827s group electrical characteristics 15.6.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 1. power supply voltage and oscillator frequency range 38.4 1.8 3.6 v cc (v) f w (khz) all operating modes 32.768 4.0 10.0 2.0 1.8 2.7 3.6 v cc (v) fosc (mhz) active (high-speed) mode sleep (high-speed) mode note: fosc is the oscillator frequency. when external clocks are used, fosc=1mhz is the minimum. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 467 of 626 rej09b0144-0600 2. power supply voltage and operating frequency range 16.384 8.192 4.096 1.8 3.6 v cc (v) sub (khz) 19.2 9.6 4.8 2.0 5.0 (0.5) 1.0 1.8 2.7 3.6 v cc (v) (mhz) 250 625 (7.813) 15.625 1.8 2.7 3.6 v cc (v) (khz) active (medium-speed) mode (except a/d converter) sleep (medium-speed) mode (except a/d converter) active (high-speed) mode sleep (high-speed) mode (except cpu) subactive mode subsleep mode (except cpu) watch mode (except cpu) figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =1mhz. note: figures in parentheses are the minimum operating frequency of a case external clocks are used. when using an oscillator, the minimum operating frequency is =15.625khz. note: 3. analog power supply voltage and a/d converter operating range 625 500 1.8 2.7 3.6 av cc (v) (khz) 5.0 1.0 0.5 1.8 2.7 3.6 av cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode active (medium-speed) mode sleep (medium-speed) mode section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 468 of 626 rej09b0144-0600 15.6.2 dc characteristics table 15.16 lists the dc characteristics of the h8/3827s group. table 15.16 dc characteristics values item symbol applicable pins min typ max unit test condition notes input high voltage v ih res , wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig sck 31 , sck 32 , adtrg 0.9 v cc ?v cc + 0.3 v rxd 31 , rxd 32 , ud 0.8 v cc ?v cc + 0.3 v osc 1 0.9 v cc ?v cc + 0.3 v x 1 0.9 v cc ?v cc + 0.3 v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.8 v cc ?v cc + 0.3 v pb 0 to pb 7 0.8 v cc ?av cc + 0.3 note: connect the test pin to v ss . section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 469 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes input low voltage v il res , wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig sck 31 , sck 32 , adtrg ?0.3 ? 0.1 v cc v rxd 31 , rxd 32 , ud ?0.3 ? 0.2 v cc v osc 1 ?0.3 ? 0.1 v cc v x 1 ?0.3 ? 0.1 v cc v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 , pb 0 to pb 7 ?0.3 ? 0.2 v cc v output high voltage v oh p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc ? 0.3 ? ? v ?i oh = 0.1 ma section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 470 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes output low voltage v ol p1 0 to p1 7 , p4 0 to p4 2 ??0.5 vi ol = 0.4 ma p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 ??0.5 i ol = 0.4 ma p3 0 to p3 7 ??0.5 i ol = 0.4 ma input/output leakage current | i il | res , osc 1 , x 1 , p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 ??1.0 av in = 0.5 v to v cc ? 0.5 v pb 0 to pb 7 ??1.0 v in = 0.5 v to av cc ? 0.5 v pull-up mos current ?i p p1 0 to p1 7 , p3 0 to p3 7 , p5 0 to p5 7 , p6 0 to p6 7 10.0 ? 300.0 a v cc = 3 v, v in = 0 v section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 471 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes input capacitance c in all input pins except power supply ? ? 15.0 pf f = 1mhz, v in =0 v, t a = 25c active mode current dissipation i ope1 v cc ? 0.4 * 3 ma active (high-speed) mode v cc = 1.8 v, f osc = 2 mhz * 1 * 2 ? 1.4 * 3 active (high-speed) mode v cc = 3 v, f osc = 4 mhz ? 3.5 5.5 active (high-speed) mode v cc = 3 v, f osc = 10 mhz i ope2 v cc ? 0.1 * 3 active (medium-speed) mode v cc = 1.8 v, f osc = 2 mhz osc /128 ? 0.3 * 3 active (medium-speed) mode v cc = 3 v, f osc = 4 mhz osc /128 ? 0.7 1.6 active (medium-speed) mode v cc = 3 v, f osc = 10 mhz osc /128 i sleep v cc ? 0.2 * 3 ma v cc = 1.8 v, f osc = 2 mhz * 1 * 2 sleep mode current dissipation ? 0.6 * 3 v cc = 3 v, f osc = 4 mhz ? 1.4 2.9 v cc = 3 v, f osc = 10 mhz section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 472 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes subactive mode current dissipation i sub v cc ?8 * 3 a v cc = 1.8 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 1 * 2 ?4 * 3 v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /8) ?14 * 3 v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) subsleep mode current dissipation i subsp v cc ?5.012 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 1 * 2 watch mode current dissipation i watch v cc ?1.4 * 3 a v cc = 1.8 v, ta = 25 c 32 khz crystal oscillator lcd not used * 1 * 2 ?2.2 * 3 v cc = 2.7 v, ta = 25 c 32 khz crystal oscillator lcd not used ?2.86 v cc = 2.7 v, 32 khz crystal oscillator lcd not used standby mode current dissipation i stby v cc ?0.3 * 3 a 32 khz crystal oscillator not used v cc = 1.8 v, ta = 25 c * 1 * 2 ?0.5 * 3 32 khz crystal oscillator not used v cc = 2.7 v, ta = 25 c ? 1 5 except the above ram data retaining voltage v ram v cc 1.5 ? ? v section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 473 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes allowable output low current (per pin) i ol all output pins ? ? 0.5 ma allowable output low current (total) i ol all output pins ? ? 20.0 ma allowable output high current (per pin) ?i oh all output pins ? ? 0.2 ma allowable output high current (total) ? i oh all output pins ? ? 10.0 ma notes: 1. pin states during current measurement. mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) v cc only cpu operates v cc halted active (medium- speed) mode (i ope2 ) sleep mode v cc only timers operate v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd subactive mode v cc only cpu operates v cc halted subsleep mode v cc only timers operate, cpu stops v cc halted watch mode v cc only time base operates, cpu stops v cc halted system clock oscillator: crystal subclock oscillator: crystal standby mode v cc cpu and timers both stop v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd 2. excludes current in pull-up mos transistors and output buffers. 3. the maximum current consumption value (standard) is 1.1 typ. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 474 of 626 rej09b0144-0600 15.6.3 ac characteristics table 15.17 lists the control signal timing, and tables 15.18 lists the serial interface timing of the h8/3827s. table 15.17 control signal timing values item symbol applicable pins min typ max unit test condition reference figure f osc osc 1 , osc 2 2? 10mhzv cc = 2.7 v to 3.6 v system clock oscillation frequency 2? 4 v cc = 1.8 v to 3.6 v osc clock ( osc ) cycle time t osc osc 1 , osc 2 100 ? 500 (1000) ns v cc = 2.7 v to 3.6 v figure 15.1 250 ? 500 (1000) v cc = 1.8 v to 3.6 v * 2 t cyc 2 ? 128 t osc system clock ( ) cycle time ? ? 128 s subclock oscillation frequency f w x 1 , x 2 ? 32.768 or 38.4 ?khz watch clock ( w ) cycle time t w x 1 , x 2 ? 30.5 or 26.0 ? s figure 15.1 subclock ( sub ) cycle time t subcyc 2? 8 t w * 1 instruction cycle time 2? ?t cyc t subcyc section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 475 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition reference figure oscillation stabilization time t rc osc 1 , osc 2 ? 20 45 s ceramic oscillator parameters v cc = 2.2 v to 3.6 v figure 15.9 ? 80 ? ceramic oscillator parameters except the above ? 0.8 2 ms crystal oscillator parameters v cc = 2.7 v to 3.6 v ? 1.2 3 crystal oscillator parameters v cc = 2.2 v to 3.6 v ? 4.0 ? crystal oscillator parameters except the above ? ? 50 except the above x1, x2 ? ? 2 s v cc = 2.2 v to 3.6 v ? 4 ? except the above t cph osc 1 40 ? ? ns v cc = 2.7 v to 3.6 v figure 15.1 100 ? ? v cc = 1.8 v to 3.6 v external clock high width x 1 ? 15.26 or 13.02 ?s t cpl osc 1 40 ? ? ns v cc = 2.7 v to 3.6 v figure 15.1 100 ? ? v cc = 1.8 v to 3.6 v external clock low width x 1 ? 15.26 or 13.02 ?s t cpr osc 1 ? ? 10 ns v cc = 2.7 v to 3.6 v figure 15.1 ?? 25 v cc = 1.8 v to 3.6 v external clock rise time x 1 ? ? 55.0 t cpf osc 1 ? ? 10 ns v cc = 2.7 v to 3.6 v figure 15.1 ?? 25 v cc = 1.8 v to 3.6 v external clock fall time x 1 ? ? 55.0 pin res low width t rel res 10 ? ? t cyc figure 15.2 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 476 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition reference figure input pin high width t ih irq 0 to irq 4 , wkp 0 to wkp 7 adtrg , tmic tmif, tmig, aevl, aevh 2? ?t cyc t subcyc figure 15.3 input pin low width t il irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmic, tmif, tmig, aevl, aevh 2? ?t cyc t subcyc figure 15.3 ud pin minimum modulation width t udh t udl ud 4 ? ? t cyc t subcyc figure 15.4 notes: 1. selected with sa1 and sa0 of system clock control register 2 (syscr2). 2. figures in parentheses are the maximum t osc rate with external clock input. table 15.18 serial interface (sci3-1, sci3-2) timing values item symbol min typ max unit test conditions reference figure asynchronous t scyc 4 ? ? figure 15.5 input clock cycle synchronous 6 ? ? t cyc or t subcyc input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 15.5 transmit data delay time (synchronous) t txd ??1t cyc or t subcyc figure 15.6 receive data setup time (synchronous) t rxs 400.0 ? ? ns figure 15.6 receive data hold time (synchronous) t rxh 400.0 ? ? ns figure 15.6 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 477 of 626 rej09b0144-0600 15.6.4 a/d converter characteristics table 15.19 shows the a/d converter characteristics. table 15.19 a/d converter characteristics values item symbol applicable pins min typ max unit test condition notes analog power supply voltage av cc av cc 1.8 ? 3.6 v * 1 analog input voltage av in an 0 to an 7 ? 0.3 ? av cc + 0.3 v ai ope av cc ??1.2 maav cc = 3.0 v analog power supply current ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ??5 a * 3 analog input capacitance c ain an 0 to an 7 ? ? 15.0 pf allowable signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bit nonlinearity error ??3.5 lsbav cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v ??5.5 av cc = 2.0 v to 3.6 v v cc = 2.0 v to 3.6 v ? ? 7.5 except the above * 4 quantization error ??0.5 lsb section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 478 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes absolute accuracy ?24 lsbav cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v ?2.56 av cc = 2.0 v to 3.6 v v cc = 2.0 v to 3.6 v ? 3 8 except the above * 4 conversion time 12.4 ? 124 s av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v 62 ? 124 except the above notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 4. conversion time 62 s section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 479 of 626 rej09b0144-0600 15.6.5 lcd characteristics table 15.20 shows the lcd characteristics. table 15.20 lcd characteristics values item symbol applicable pins test conditions min typ max unit notes segment driver drop voltage v ds seg 1 to seg 32 i d = 2 a v 1 = 2.7 to 3.6 v ??0.6v * 1 common driver drop voltage v dc com 1 to com 4 i d = 2 a v 1 = 2.7 to 3.6 v ??0.3v * 1 lcd power supply split-resistance r lcd between v 1 and v ss 1.5 3.5 7 m ? liquid crystal display voltage v lcd v 1 2.2 ? 3.6 v * 2 notes: 1. the voltage drop from power supply pins v 1 , v 2 , v 3 , and v ss to each segment pin or common pin. 2. when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v 1 v 2 v 3 v ss . table 15.21 ac characteristics for external segment expansion values item symbol applicable pins test conditions min typ max unit reference figure clock high width t cwh cl 1 , cl 2 * 800.0 ? ? ns figure 15.7 clock low width t cwl cl 2 * 800.0 ? ? ns figure 15.7 clock setup time t csu cl 1 , cl 2 * 500.0 ? ? ns figure 15.7 data setup time t su do * 300.0 ? ? ns figure 15.7 data hold time t dh do * 300.0 ? ? ns figure 15.7 m delay time t dm m ?1000.0 ? 1000.0 ns figure 15.7 clock rise and fall times t ct cl 1 , cl 2 ? ? 170.0 ns figure 15.7 note: * value when the frame frequency is set to between 30.5 hz and 488 hz. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 480 of 626 rej09b0144-0600 15.7 absolute maximum ratings of h8/38327 group and h8/38427 group table 15.22 lists the absolute maximum ratings. table 15.22 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +7.0 v * 1 cv cc ?0.3 to +4.3 v analog power supply voltage av cc ?0.3 to +7.0 v input voltage other than port b v in ?0.3 to v cc +0.3 v port b av in ?0.3 to av cc +0.3 v operating temperature t opr ?20 to +75 * 2 (regular specifications) c ?40 to +85 * 2 (wide-range temperature specifications) +75 * 3 (chip shipment specifications) storage temperature t stg ?55 to +125 c notes: 1. permanent damage may result if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 2. the operating temperature ranges from ?20 c to +75 c when programming or erasing the flash memory. 3. the temperature range in which power may be applied to the device is ?20 c to +75 c. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 481 of 626 rej09b0144-0600 15.8 electrical characteristics of h8/38327 group and h8/38427 group 15.8.1 power supply voltage and operating ranges the power supply voltage and operating ranges (shaded portions) are shown below. 1. power supply voltage and oscillation frequency range 5.5 v cc (v) f w (khz) all operating modes 32.768 38.4 2.7 5.5 v cc (v) f w (khz) all operating modes 32.768 38.4 2.7 2.0 16.0 2.7 5.5 v cc (v) fosc (mhz) active (high-speed) mode sleep (high-speed) mode h8/38327 group 2.0 10.0 16.0 2.7 5.5 4.5 v cc (v) fosc (mhz) active (high-speed) mode sleep (high-speed) mode h8/38427 group note: fosc is the oscillator frequency. when an external clock is used 1 mhz is the minimum fosc value. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 482 of 626 rej09b0144-0600 2. power supply voltage and operating frequency range ? subactive mode subsleep mode (except cpu) watch mode (except cpu) 16.384 8.192 4.096 2.7 5.5 v cc (v) sub (khz) 19.2 9.6 4.8 subactive mode subsleep mode (except cpu) watch mode (except cpu) 16.384 8.192 4.096 2.7 5.5 v cc (v) sub (khz) 19.2 9.6 4.8 8.0 (0.5) * 1 1.0 2.7 5.5 v cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode (except cpu) 1000 (7.813) * 2 15.625 2.7 5.5 v cc (v) (khz) active (medium-speed) mode sleep (medium-speed) mode (except a/d converter) notes 1. the figure in parentheses ( ) indicates the minimum operating frequency when an external clock is used. when the resonator is used the minimum operating frequency ( ) is 1 mhz. 2. the figure in parentheses ( ) indicates the minimum operating frequency when an external clock is used. when the resonator is used the minimum operating frequency ( ) is 15.625 khz. h8/38327 group 8.0 5.0 (0.5) * 1 1.0 2.7 5.5 4.5 v cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode (except cpu) 1000 625 (7.813) * 2 15.625 2.7 5.5 4.5 v cc (v) (khz) active (medium-speed) mode sleep (medium-speed) mode (except a/d converter) h8/38427 group section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 483 of 626 rej09b0144-0600 3. analog power supply voltage and a/d converter operating range 8.0 0.5 1.0 2.7 5.5 av cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode 1000 500 2.7 5.5 av cc (v) (khz) active (medium-speed) mode sleep (medium-speed) mode h8/38327 group 5.0 (0.5) 1.0 2.7 5.5 av cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode 1000 625 500 2.7 5.5 4.5 av cc (v) (khz) active (medium-speed) mode sleep (medium-speed) mode h8/38427 group section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 484 of 626 rej09b0144-0600 15.8.2 dc characteristics table 15.23 lists the dc characteristics. table 15.23 dc characteristics v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, unless otherwise specified values item symbol applicable pins min typ max unit test condition notes input high voltage v ih v cc 0.8 ? v cc + 0.3 v v cc = 4.0 v to 5.5 v res , wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig, adtrg, sck 31 , sck 32 v cc 0.9 ? v cc + 0.3 other than above v cc 0.7 ? v cc + 0.3 v v cc = 4.0 v to 5.5 v rxd 31 , rxd 32 , ud v cc 0.8 ? v cc + 0.3 other than above osc 1 v cc 0.8 ? v cc + 0.3 v v cc = 4.0 v to 5.5 v v cc 0.9 ? v cc + 0.3 other than above v cc 0.7 ? v cc + 0.3 v v cc = 4.0 v to 5.5 v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc 0.8 ? v cc + 0.3 other than above pb 0 to pb 7 v cc 0.7 ? av cc + 0.3 v v cc = 4.0 v to 5.5 v v cc 0.8 ? av cc + 0.3 other than above excl v cc 0.9 ? v cc + 0.3 v note: connect the test pin to v ss . section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 485 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes input low voltage v il ? 0.3 ? v cc 0.2 v v cc = 4.0 v to 5.5 v res , wkp 0 to wkp 7 , irq 0 to irq 4 , aevl, aevh, tmic, tmif, tmig, adtrg, sck 31 , sck 32 ? 0.3 ? v cc 0.1 other than above ? 0.3 ? v cc 0.3 v v cc = 4.0 v to 5.5 v rxd 31 , rxd 32 , ud ? 0.3 ? v cc 0.2 other than above osc 1 ? 0.3 ? v cc 0.2 v v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.1 other than above excl ? 0.3 ? 0.1 v cc v ? 0.3 ? v cc 0.3 v v cc = 4.0 v to 5.5 v p1 0 to p1 7 p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 , pb 0 to pb 7 ? 0.3 ? v cc 0.2 other than above v oh v cc ? 1.0 ? ? v v cc = 4.0 v to 5.5 v ?i oh = 1.0 ma output high voltage v cc ? 0.5 ? ? v cc = 4.0 v to 5.5 v ?i oh = 0.5 ma p1 0 to p1 7 p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc ? 0.3 ? ? ?i oh = 0.1 ma section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 486 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes output low voltage v ol ??0.6vv cc = 4.0 v to 5.5 v i ol = 1.6 ma p1 0 to p1 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 ??0.5 i ol = 0.4 ma p3 0 to p3 7 ??1.0 v cc = 4.0 v to 5.5 v i ol = 10 ma ??0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma ??0.5 i ol = 0.4 ma | i il | res , p4 3 , p1 0 to p1 7 , osc 1 , x 1 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 ??1.0av in = 0.5 v to v cc ? 0.5 v input/ output leakage current pb 0 to pb 7 ??1.0 v in = 0.5 v to av cc ? 0.5 v ?i p 20 ? 200 a v cc = 5.0 v, v in = 0.0 v pull-up mos current p1 0 to p1 7 , p3 0 to p3 7 , p5 0 to p5 7 , p6 0 to p6 7 ?40? v cc = 2.7 v, v in = 0.0 v refer- ence value input capaci- tance c in all input pins except power supply pin ? ? 15.0 pf f = 1 mhz, v in = 0.0 v, t a = 25c section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 487 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes active mode current consump- tion i ope1 v cc ? 0.8 ? ma active (high-speed) mode v cc = 2.7 v, f osc = 2 mhz * 1 * 3 * 4 approx. max. value = 1.1 typ. ?1.2? * 2 * 3 * 4 approx. max. value = 1.1 typ. ? 1.0 ? active (high-speed) mode v cc = 5 v, f osc = 2 mhz * 1 * 3 * 4 approx. max. value = 1.1 typ. ?1.5? * 2 * 3 * 4 approx. max. value = 1.1 typ. ? 2.0 ? active (high-speed) mode v cc = 5 v, f osc = 4 mhz * 1 * 3 * 4 approx. max. value = 1.1 typ. ?2.4? * 2 * 3 * 4 ?4.07.0 * 1 * 3 * 4 ?4.97.0 active (high-speed) mode v cc = 5 v, f osc = 10 mhz * 2 * 3 * 4 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 488 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes active mode current consump- tion i ope2 v cc ? 0.4 ? ma active (medium- speed) mode v cc = 2.7 v, f osc = 2 mhz, osc /128 * 1 * 3 * 4 approx. max. value = 1.1 typ. ?0.7? * 2 * 3 * 4 approx. max. value = 1.1 typ. ? 0.5 ? active (medium- speed) mode v cc = 5 v, f osc = 2 mhz, osc /128 * 1 * 3 * 4 approx. max. value = 1.1 typ. ?1.0? * 2 * 3 * 4 approx. max. value = 1.1 typ. ? 0.8 ? active (medium- speed) mode v cc = 5 v, f osc = 4 mhz, osc /128 * 1 * 3 * 4 approx. max. value = 1.1 typ. ?1.2? * 2 * 3 * 4 ?1.23.0 * 1 * 3 * 4 ?1.73.0 active (medium- speed) mode v cc = 5 v, f osc = 10 mhz, osc /128 * 2 * 3 * 4 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 489 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes sleep mode current consump- tion i sleep v cc ?0.5?mav cc = 2.7 v, f osc = 2 mhz * 1 * 3 * 4 approx. max. value = 1.1 typ. ?0.8? * 2 * 3 * 4 approx. max. value = 1.1 typ. ?0.7? v cc = 5 v, f osc = 2 mhz * 1 * 3 * 4 approx. max. value = 1.1 typ. ?1.2? * 2 * 3 * 4 approx. max. value = 1.1 typ. ?1.1? v cc = 5 v, f osc = 4 mhz * 1 * 3 * 4 approx. max. value = 1.1 typ. ?1.6? * 2 * 3 * 4 ?1.95.0 * 1 * 3 * 4 ?2.65.0 v cc = 5 v, f osc = 10 mhz * 2 * 3 * 4 i sub v cc ?12?a * 1 * 3 * 4 reference value subactive mode current consump- tion ?15? v cc = 2.7 v, lcd on, 32-khz crystal resonator used ( sub = w /8) * 2 * 3 * 4 reference value ?1850 * 1 * 3 * 4 ?3050 v cc = 2.7 v, lcd on, 32-khz crystal resonator used ( sub = w /2) * 2 * 3 * 4 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 490 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes subsleep mode current consump- tion i subsp v cc ?3.816av cc = 2.7 v, lcd on, 32-khz crystal resonator used ( sub = w /2) * 3 * 4 i watch v cc ?1.8?a * 1 * 3 * 4 reference value watch mode current consump- tion ?1.8? v cc = 2.7 v, t a = 25 c, 32-khz crystal resonator used, lcd not used * 2 * 3 * 4 reference value ?3.06.0 v cc = 2.7 v, 32-khz crystal resonator used, lcd not used * 3 * 4 i stby v cc ?0.3?av cc = 2.7 v, t a = 25 c, 32-khz crystal resonator not used * 1 * 3 * 4 reference value standby mode current consump- tion ?0.3? v cc = 2.7 v, t a = 25 c, 32-khz crystal resonator not used * 2 * 3 * 4 reference value ?0.4? * 1 * 3 * 4 reference value ?0.5? v cc = 5.0 v, t a = 25 c, 32-khz crystal resonator not used * 2 * 3 * 4 reference value ? 1.0 5.0 32-khz crystal resonator not used * 3 * 4 ram data retaining voltage v ram v cc 2.0 ? ? v * 5 i ol output pins except port 3 ??2.0mav cc = 4.0 v to 5.5 v port 3 ? ? 10.0 v cc = 4.0 v to 5.5 v allowable output low current (per pin) all output pins ? ? 0.5 i ol output pins except port 3 ? ? 40.0 ma v cc = 4.0 v to 5.5 v port 3 ? ? 80.0 v cc = 4.0 v to 5.5 v allowable output low current (total) all output pins ? ? 20.0 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 491 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition notes ?i oh all output pins ? ? 2.0 ma v cc = 4.0 v to 5.5 v allowable output high current (per pin) ? ? 0.2 other than above ?i oh all output pins ? ? 15.0 ma v cc = 4.0 v to 5.5 v allowable output high current (total) ? ? 10.0 other than above notes: connect the test pin to v ss . 1. applies to the mask-rom version. 2. applies to the f-ztat version. 3. pin states when current consumption is measured mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) active (medium- speed) mode (i ope2 ) v cc only cpu operates v cc stops sleep mode v cc only all on-chip timers operate v cc stops system clock: crystal resonator subclock: pin x 1 = gnd subactive mode v cc only cpu operates v cc stops subsleep mode v cc only all on-chip timers operate cpu stops v cc stops watch mode v cc only clock time base operates cpu stops v cc stops system clock: crystal resonator subclock: crystal resonator standby mode v cc cpu and timers both stop v cc stops system clock: crystal resonator subclock: pin x 1 = gnd 4. except current which flows to the pull-up mos or output buffer 5. voltage maintained in standby mode section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 492 of 626 rej09b0144-0600 15.8.3 ac characteristics table 15.24 lists the control signal timing and table 15.25 lists the serial interface timing. table 15.24 control signal timing v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, unless otherwise specified values item symbol applicable pins min typ max unit test condition reference figure 2.0 ? 16.0 mhz * 3 2.0 ? 16.0 v cc = 4.5 to 5.5 v system clock oscillation frequency f osc osc 1 , osc 2 2.0 ? 10.0 v cc = 2.7 to 5.5 v * 4 62.5 ? 500 (1000) ns figure 15.1 * 2 * 3 62.5 ? 500 (1000) v cc = 4.5 to 5.5 v osc clock ( osc ) cycle time t osc osc 1 , osc 2 100 ? 500 (1000) v cc = 2.7 to 5.5 v figure 15.1 * 2 * 4 t cyc 2 ? 128 t osc system clock ( ) cycle time ? ? 128 s subclock oscillation frequency f w x 1 , x 2 , excl ? 32.768 or 38.4 ?khz watch clock ( w ) cycle time t w x 1 , x 2 , excl ? 30.5 or 26.0 ? s figure 15.1 subclock ( sub ) cycle time t subcyc 2? 4 t w * 1 instruction cycle time 2? ? t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 ? 20 45 s ceramic resonator (v cc = 3.0 to 5.5 v) ? 80 ? ceramic resonator other than above ? 0.8 2 ms crystal resonator figure 15.10 ? ? 50 other than above t rc x 1 , x 2 ?? 2.0 s section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 493 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition reference figure external clock high width t cph osc 1 25 ? ? ns figure 15.1 * 3 25 ? ? v cc = 4.5 to 5.5 v 40 ? ? v cc = 2.7 to 5.5 v figure 15.1 * 4 excl ? 15.26 or 13.02 ? s figure 15.1 external clock low width t cpl osc 1 25 ? ? ns figure 15.1 * 3 25 ? ? v cc = 4.5 to 5.5 v 40 ? ? v cc = 2.7 to 5.5 v figure 15.1 * 4 excl ? 15.26 or 13.02 ? s figure 15.1 external clock rise time t cpr osc 1 ? ? 6 ns figure 15.1 * 3 ?? 6 v cc = 4.5 to 5.5 v ?? 10 v cc = 2.7 to 5.5 v figure 15.1 * 4 excl ? ? 55.0 figure 15.1 external clock fall time t cpf osc 1 ? ? 6 ns figure 15.1 * 3 ?? 6 v cc = 4.5 to 5.5 v ?? 10 v cc = 2.7 to 5.5 v figure 15.1 * 4 excl ? ? 55.0 figure 15.1 res pin low width t rel res 10 ? ? t cyc figure 15.2 input pin high width t ih irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmic, tmif, tmig 2? ? t cyc t subcyc figure 15.3 aevl, aevh 32 ? ? ns section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 494 of 626 rej09b0144-0600 values item symbol applicable pins min typ max unit test condition reference figure input pin low width t il irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmic, tmif, tmig 2? ? t cyc t subcyc figure 15.3 aevl, aevh 32 ? ? ns ud pin minimum transition width t udh t udl ud 4 ? ? t cyc t subcyc figure 15.4 notes: 1. determined by the sa1 and sa0 bits in the system control register 2 (syscr2). 2. the figure in parentheses ( ) indicates the maximum fosc value when an external clock is used. 3. also applies to h8/38327 group. 4. also applies to h8/38427 group. table 15.25 serial interface (sci3) timing v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, unless otherwise specified values item symbol min typ max unit test condition reference figure asynchronous t scyc 4 ? ? figure 15.5 input clock cycle clocked synchronous 6 ? ? t cyc or t subcyc input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 15.5 transmit data delay time (clocked synchronous) t txd ??1t cyc or t subcyc figure 15.6 receive data setup time (clocked synchronous) t rxs 200 ? ? ns figure 15.6 receive data hold time (clocked synchronous) t rxh 200 ? ? ns figure 15.6 section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 495 of 626 rej09b0144-0600 15.8.4 a/d converter characteristics table 15.26 shows the a/d converter characteristics. table 15.26 a/d converter characteristics v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, unless otherwise specified values item symbol applicable pins min typ max unit test condition reference figure analog power supply voltage av cc av cc 2.7 ? 5.5 v * 1 analog input voltage av in an 0 to an 3 ? 0.3 ? av cc + 0.3 v ai ope av cc ??1.5 maav cc = 5.0 v analog power supply current ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ??5.0 a * 3 analog input capacitance c ain an 0 to an 7 ? ? 15.0 pf allowable signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bit nonlinearity error ? ? 3.5 lsb av cc = 4.0 v to 5.5 v ??7.5 av cc = 2.7 v to 5.5 v quantization error ? ? 0.5 lsb absolute accuracy ? 2.0 4.0 lsb av cc = 4.0 v to 5.5 v ? 2.0 8.0 av cc = 2.7 v to 5.5 v conversion time 7.8 ? 124 s * 4 12.4 ? 124 * 5 notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 4. also applies to h8/38327 group. 5. also applies to h8/38427 group. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 496 of 626 rej09b0144-0600 15.8.5 lcd characteristics table 15.27 shows the lcd characteristics. table 15.27 lcd characteristics v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, unless otherwise specified values item symbol applicable pins min typ max unit test condition reference figure segment driver step-down voltage v ds seg 1 to seg 32 ??0.6vi d = 2 a v1 = 2.7 v to 5.5 v * 1 common driver step-down voltage v dc com 1 to com 4 ??0.3vi d = 2 a v1 = 2.7 v to 5.5 v * 1 lcd power supply split-resistance r lcd 1.5 3.0 7.0 m ? between v1 and v ss liquid crystal display voltage v lcd v 1 2.7 ? 5.5 v * 2 notes: 1. the voltage step-down from power supply pins v1, v2, v3, and v ss to each segment pin or common pin. 2. when the liquid crystal display voltage is supplied from an external power supply, ensure that the following relationship is maintained: v1 v2 v3 v ss . section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 497 of 626 rej09b0144-0600 15.8.6 flash memory characteristics table 15.28 flash memory characteristics condition: av cc = 2.7 v to 5.5 v, v ss = av ss = 0.0 v, v cc = 2.7 v to 5.5 v (range of operating voltage when reading), v cc = 3.0 v to 5.5 v (range of operating voltage when programming/erasing), t a = ?20c to +75c (range of operating temperature when programming/erasing: product with regular specifications, product with wide-range temperature specifications) values item symbol min typ max unit test conditions programming time * 1 * 2 * 4 t p ? 7 200 ms/128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block reprogramming count n wec 1000 * 8 10000 * 9 ?times data retain period t drp 10 * 10 ??year programming wait time after swe-bit setting * 1 x 1 ??s wait time after psu-bit setting * 1 y 50??s z1 28 30 32 s 1 n 6 z2 198 200 202 s 7 n 1000 wait time after p-bit setting * 1 * 4 z3 8 10 12 s additional programming wait time after p-bit clear * 1 5 ??s wait time after psu-bit clear * 1 5 ??s wait time after pv-bit setting * 1 4 ??s wait time after dummy write * 1 2 ??s wait time after pv-bit clear * 1 2 ??s wait time after swe-bit clear * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 498 of 626 rej09b0144-0600 values item symbol min typ max unit test conditions wait time after swe-bit setting * 1 x 1 ??s wait time after esu-bit setting * 1 y 100 ? ? s wait time after e-bit setting * 1 * 6 z 10 ? 100 ms wait time after e-bit clear * 1 10??s wait time after esu-bit clear * 1 10??s wait time after ev-bit setting * 1 20??s wait time after dummy write * 1 2 ??s wait time after ev-bit clear * 1 4 ??s wait time after swe-bit clear * 1 100 ? ? s erase maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. set the times according to the program/erase algorithms. 2. programming time per 128 bytes (shows the total period for which the p bit in flmcr1 is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e bit in flmcr1 is set. it does not include the erase verification time.) 4. maximum programming time (t p (max)) t p (max) = wait time after p-bit setting (z) maximum number of writes (n) 5. the maximum number of writes (n) should be set according to the actual set value of z1, z2, and z3 to allow programming within the maximum programming time (t p (max)). the wait time after p-bit setting (z1 and z2) should be alternated according to the number of writes (n) as follows: 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. maximum erase time (t e (max)) t e (max) = wait time after e-bit setting (z) maximum erase count (n) 7. the maximum number of erases (n) should be set according to the actual set value of z to allow erasing within the maximum erase time (t e (max)). 8. this minimum value guarantees all characteristics after reprogramming (the guaranteed range is from 1 to the minimum value). 9. reference value when the temperature is 25 c (normally reprogramming will be performed by this count). 10. this is a data retain characteristic when reprogramming is performed within the specification range including this minimum value. section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 499 of 626 rej09b0144-0600 15.9 operation timing figures 15.1 to 15.7 show timing diagrams. t , tw osc v ih v il t cph t cpl t cpr osc1 x 1 t cpf figure 15.1 clock input timing res v il t rel figure 15.2 res res res res low width v ih v il t il irq 0 to irq 4 , wkp 0 to wkp 7 , adtrg , tmic, tmif, tmig, aevl, aevh t ih figure 15.3 input timing section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 500 of 626 rej09b0144-0600 t udl v ih v il t udh ud figure 15.4 ud pin minimum modulation width timing t scyc 31 t sckw sck 32 sck figure 15.5 sck3 input clock timing section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 501 of 626 rej09b0144-0600 32 t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * v ol oh ol sck 31 sck txd 31 txd 32 (transmit data) rxd 31 rxd 32 (receive data) note: * output timing reference levels output high output low load conditions are shown in figure 15.8. v = 1/2vcc + 0.2 v v = 0.8 v figure 15.6 sci3 synchronous mode input/output timing section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 502 of 626 rej09b0144-0600 cl 1 cl 2 do m t su t ct t dh t cwl t cwh t cwh t csu t ct t csu t dm v cc ? 0.5v v cc ? 0.5v 0.4v 0.4v 0.4v v cc ? 0.5v 0.4v figure 15.7 segment expansion signal timing section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 503 of 626 rej09b0144-0600 15.10 output load circuit v cc 2.4 k ? 12 k ? 30 pf output pin figure 15.8 output load condition 15.11 resonator c s c o r s c o 4 mhz manufacturer's publicly released values max. 8.8 max. 36 pf manufacturer murata products name cstls 4m00g 53/56 ceramic oscillator parameters r s osc 2 osc 1 l s frequency r s c o 4.193 mhz manufacturer's publicly released values max. 100 max. 16 pf manufacturer nihon denpa kogyo products name nr-18 frequency crystal oscillator parameters figure 15.9 resonator equivalent circuit section 15 electrical characteristics rev. 6.00 aug 04, 2006 page 504 of 626 rej09b0144-0600 resonating frequency manufacturer model c 1 , c 2 murata 2 mhz cstcc2m00g53-b0 15pf 20% cstcc2m00g56-b0 47pf 20% cstls4m00g53-b0 15pf 20% cstls4m00g56-b0 47pf 20% cstls10m0g53-b0 15pf 20% cstls10m0g56-b0 47pf 20% 4 mhz 10 mhz ceramic resonator resonating frequency manufacturer model c 1 , c 2 nihon denpa kogyo 4 mhz nr-18 12pf 20% 10 mhz crystal resonator figure 15.10 resonator equivalent circuit 15.12 usage note each of the products covered in this manual satisfy the electrical characteristics indicated. however, the actual electrical characteristics, operating margin and noise margin may differ from the indicated values due to differences in the manufacturing process, built-in rom, layout pattern and other factors. if a system evaluation test is conducted with the ztat or f-ztat version, when switching to a mask rom version, perform the same evaluation test with the mask rom version. appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 505 of 626 rej09b0144-0600 appendix a cpu instruction set a.1 instructions operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx: 3/8/16 immediate data (3, 8, or 16 bits) d: 8/16 displacement (8 or 16 bits) @aa: 8/16 absolute address (8 or 16 bits) + addition ? subtraction multiplication division logical and logical or exclusive logical or move ? logical complement condition code notation symbol ? modified according to the instruction result * not fixed (value not guaranteed) 0 always cleared to 0 ? not affected by the instruction execution result appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 506 of 626 rej09b0144-0600 table a.1 lists the h8/300l cpu instruction set. table a.1 instruction set mnemonic operation i h n z v c mov.b #xx:8, rd b #xx:8 rd8 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0?2 mov.b rs, rd b rs8 rd8 2 ? ? 0 ? 2 mov.b @rs, rd b @rs16 rd8 2 ? ? 0 ? 4 mov.b @(d:16, rs), rd b @(d:16, rs16) rd8 4 ? ? 0 ? 6 mov.b @rs+, rd b @rs16 rd8 2 ? ? 0 ? 6 rs16+1 rs16 mov.b @aa:8, rd b @aa:8 rd8 2 ? ? 0 ? 4 mov.b @aa:16, rd b @aa:16 rd8 4 ? ? 0 ? 6 mov.b rs, @rd b rs8 @rd16 2 ? ? 0 ? 4 mov.b rs, @(d:16, rd) b rs8 @(d:16, rd16) 4 ? ? 0 ? 6 mov.b rs, @?rd b rd16?1 rd16 2 ? ? 0 ? 6 rs8 @rd16 mov.b rs, @aa:8 b rs8 @aa:8 2 ? ? 0 ? 4 mov.b rs, @aa:16 b rs8 @aa:16 4 ? ? 0 ? 6 mov.w #xx:16, rd w #xx:16 rd 4 ? ? 0 ? 4 mov.w rs, rd w rs16 rd16 2 ? ? 0 ? 2 mov.w @rs, rd w @rs16 rd16 2 ? ? 0 ? 4 mov.w @(d:16, rs), rd w @(d:16, rs16) rd16 4 ? ? 0 ? 6 mov.w @rs+, rd w @rs16 rd16 2 ? ? 0 ? 6 rs16+2 rs16 mov.w @aa:16, rd w @aa:16 rd16 4 ? ? 0 ? 6 mov.w rs, @rd w rs16 @rd16 2 ? ? 0 ? 4 mov.w rs, @(d:16, rd) w rs16 @(d:16, rd16) 4 ? ? 0 ? 6 mov.w rs, @?rd w rd16?2 rd16 2 ? ? 0 ? 6 rs16 @rd16 mov.w rs, @aa:16 w rs16 @aa:16 4 ? ? 0 ? 6 pop rd w @sp rd16 2 ? ? 0 ? 6 sp+2 sp push rs w sp?2 sp 2 ? ? 0 ? 6 rs16 @sp #xx: 8/16 rn @rn @(d:16, rn) @?rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code o perand s ize appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 507 of 626 rej09b0144-0600 mnemonic operation i h n z v c add.b #xx:8, rd b rd8+#xx:8 rd8 2 ? 2 add.b rs, rd b rd8+rs8 rd8 2 ? 2 add.w rs, rd w rd16+rs16 rd16 2 ? (1) 2 addx.b #xx:8, rd b rd8+#xx:8 +c rd8 2 ? (2) 2 addx.b rs, rd b rd8+rs8 +c rd8 2 ? (2) 2 adds.w #1, rd w rd16+1 rd16 2 ?????? 2 adds.w #2, rd w rd16+2 rd16 2 ?????? 2 inc.b rd b rd8+1 rd8 2 ?? ? 2 daa.b rd b rd8 decimal adjust rd8 2 ? ** (3) 2 sub.b rs, rd b rd8 ? rs8 rd8 2 ? 2 sub.w rs, rd w rd16 ? rs16 rd16 2 ? (1) 2 subx.b #xx:8, rd b rd8 ? #xx:8 ? c rd8 2 ? (2) 2 subx.b rs, rd b rd8 ? rs8 ? c rd8 2 ? (2) 2 subs.w #1, rd w rd16 ? 1 rd16 2 ?????? 2 subs.w #2, rd w rd16 ? 2 rd16 2 ?????? 2 dec.b rd b rd8 ? 1 rd8 2 ?? ? 2 das.b rd b rd8 decimal adjust rd8 2 ? ** ? 2 neg.b rd b 0 ? rd rd 2 ? 2 cmp.b #xx:8, rd b rd8 ? #xx:8 2 ? 2 cmp.b rs, rd b rd8 ? rs8 2 ? 2 cmp.w rs, rd w rd16 ? rs16 2 ? (1) 2 #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code o perand s ize ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 508 of 626 rej09b0144-0600 mnemonic operation i h n z v c mulxu.b rs, rd b rd8 rs8 rd16 2 ?????? 14 divxu.b rs, rd b rd16 rs8 rd16 2 ?? (5) (6) ?? 14 (rdh: remainder, rdl: quotient) and.b #xx:8, rd b rd8 #xx:8 rd8 2 ?? 0 ? 2 and.b rs, rd b rd8 rs8 rd8 2 ?? 0 ? 2 or.b #xx:8, rd b rd8 #xx:8 rd8 2 ?? 0 ? 2 or.b rs, rd b rd8 rs8 rd8 2 ?? 0 ? 2 xor.b #xx:8, rd b rd8 #xx:8 rd8 2 ?? 0 ? 2 xor.b rs, rd b rd8 rs8 rd8 2 ?? 0 ? 2 not.b rd b rd rd 2 ?? 0 ? 2 shal.b rd b 2 ?? 2 shar.b rd b 2 ?? 02 shll.b rd b 2 ?? 02 shlr.b rd b 2 ?? 002 rotxl.b rd b 2 ?? 02 rotxr.b rd b 2 ?? 02 b 7 b 0 0 c c b 7 b 0 b 7 b 0 0 c b 7 b 0 0c c b 7 b 0 c b 7 b 0 #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code o perand s ize ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 509 of 626 rej09b0144-0600 mnemonic operation i h n z v c rotl.b rd b 2 ?? 02 rotr.b rd b 2 ?? 02 bset #xx:3, rd b (#xx:3 of rd8) 12 ?????? 2 bset #xx:3, @rd b (#xx:3 of @rd16) 14 ?????? 8 bset #xx:3, @aa:8 b (#xx:3 of @aa:8) 14 ?????? 8 bset rn, rd b (rn8 of rd8) 12 ?????? 2 bset rn, @rd b (rn8 of @rd16) 14 ?????? 8 bset rn, @aa:8 b (rn8 of @aa:8) 14 ?????? 8 bclr #xx:3, rd b (#xx:3 of rd8) 02 ?????? 2 bclr #xx:3, @rd b (#xx:3 of @rd16) 04 ?????? 8 bclr #xx:3, @aa:8 b (#xx:3 of @aa:8) 04 ?????? 8 bclr rn, rd b (rn8 of rd8) 02 ?????? 2 bclr rn, @rd b (rn8 of @rd16) 04 ?????? 8 bclr rn, @aa:8 b (rn8 of @aa:8) 04 ?????? 8 bnot #xx:3, rd b (#xx:3 of rd8) 2 ?????? 2 ( #xx:3 of rd8 ) bnot #xx:3, @rd b (#xx:3 of @rd16) 4 ?????? 8 ( #xx:3 of @rd16 ) bnot #xx:3, @aa:8 b (#xx:3 of @aa:8) 4 ?????? 8 ( #xx:3 of @aa:8 ) bnot rn, rd b (rn8 of rd8) 2 ?????? 2 ( rn8 of rd8 ) bnot rn, @rd b (rn8 of @rd16) 4 ?????? 8 ( rn8 of @rd16 ) bnot rn, @aa:8 b (rn8 of @aa:8) 4 ?????? 8 ( rn8 of @aa:8 ) #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code o perand s ize c b 7 b 0 c b 7 b 0 ? ? ? ? ? ? appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 510 of 626 rej09b0144-0600 mnemonic operation i h n z v c btst #xx:3, rd b ( #xx:3 of rd8 ) z2 ??? ?? 2 btst #xx:3, @rd b ( #xx:3 of @rd16 ) z4 ??? ?? 6 btst #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) z4 ??? ?? 6 btst rn, rd b ( rn8 of rd8 ) z2 ??? ?? 2 btst rn, @rd b ( rn8 of @rd16 ) z4 ??? ?? 6 btst rn, @aa:8 b ( rn8 of @aa:8 ) z4 ??? ?? 6 bld #xx:3, rd b (#xx:3 of rd8) c2 ????? 2 bld #xx:3, @rd b (#xx:3 of @rd16) c4 ????? 6 bld #xx:3, @aa:8 b (#xx:3 of @aa:8) c4 ????? 6 bild #xx:3, rd b ( #xx:3 of rd8 ) c2 ????? 2 bild #xx:3, @rd b ( #xx:3 of @rd16 ) c4 ????? 6 bild #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) c4 ????? 6 bst #xx:3, rd b c (#xx:3 of rd8) 2 ?????? 2 bst #xx:3, @rd b c (#xx:3 of @rd16) 4 ?????? 8 bst #xx:3, @aa:8 b c (#xx:3 of @aa:8) 4 ?????? 8 bist #xx:3, rd b c (#xx:3 of rd8) 2 ?????? 2 bist #xx:3, @rd b c (#xx:3 of @rd16) 4 ?????? 8 bist #xx:3, @aa:8 b c (#xx:3 of @aa:8) 4 ?????? 8 band #xx:3, rd b c (#xx:3 of rd8) c2 ????? 2 band #xx:3, @rd b c (#xx:3 of @rd16) c4 ????? 6 band #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 ????? 6 biand #xx:3, rd b c ( #xx:3 of rd8 ) c2 ????? 2 biand #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 ????? 6 biand #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 ????? 6 bor #xx:3, rd b c (#xx:3 of rd8) c2 ????? 2 bor #xx:3, @rd b c (#xx:3 of @rd16) c4 ????? 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 ????? 6 bior #xx:3, rd b c ( #xx:3 of rd8 ) c2 ????? 2 bior #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 ????? 6 #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code o perand s ize ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 511 of 626 rej09b0144-0600 mnemonic operation i h n z v c bior #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 ????? 6 bxor #xx:3, rd b c (#xx:3 of rd8) c2 ????? 2 bxor #xx:3, @rd b c (#xx:3 of @rd16) c4 ????? 6 bxor #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 ????? 6 bixor #xx:3, rd b c ( #xx:3 of rd8 ) c2 ????? 2 bixor #xx:3, @rd b c ( #xx:3 of @rd16 ) c4 ????? 6 bixor #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) c4 ????? 6 bra d:8 (bt d:8) ? pc pc+d:8 2 ?????? 4 brn d:8 (bf d:8) ? pc pc+2 2 ?????? 4 bhi d:8 ? c z = 0 2 ?????? 4 bls d:8 ? c z = 1 2 ?????? 4 bcc d:8 (bhs d:8) ? c = 0 2 ?????? 4 bcs d:8 (blo d:8) ? c = 1 2 ?????? 4 bne d:8 ? z = 0 2 ?????? 4 beq d:8 ? z = 1 2 ?????? 4 bvc d:8 ? v = 0 2 ?????? 4 bvs d:8 ? v = 1 2 ?????? 4 bpl d:8 ? n = 0 2 ?????? 4 bmi d:8 ? n = 1 2 ?????? 4 bge d:8 ? n v = 0 2 ?????? 4 blt d:8 ? n v = 1 2 ?????? 4 bgt d:8 ? z (n v) = 0 2 ?????? 4 ble d:8 ? z (n v) = 1 2 ?????? 4 jmp @rn ? pc rn16 2 ?????? 4 jmp @aa:16 ? pc aa:16 4 ?????? 6 jmp @@aa:8 ? pc @aa:8 2 ?????? 8 bsr d:8 ? sp ? 2 sp 2 ?????? 6 pc @sp pc pc+d:8 #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code o perand s ize if condition is true then pc pc+d:8 else next; branching condition ? ? ? ? ? ? ? appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 512 of 626 rej09b0144-0600 mnemonic operation i h n z v c jsr @rn ? sp ? 2 sp 2 ?????? 6 pc @sp pc rn16 jsr @aa:16 ? sp ? 2 sp 4 ?????? 8 pc @sp pc aa:16 jsr @@aa:8 sp ? 2 sp 2 ?????? 8 pc @sp pc @aa:8 rts ? pc @sp 2 ?????? 8 sp+2 sp rte ? ccr @sp 2 10 sp+2 sp pc @sp sp+2 sp sleep ? transit to sleep mode. 2 ?????? 2 ldc #xx:8, ccr b #xx:8 ccr 2 2 ldc rs, ccr b rs8 ccr 2 2 stc ccr, rd b ccr rd8 2 ?????? 2 andc #xx:8, ccr b ccr #xx:8 ccr 2 2 orc #xx:8, ccr b ccr #xx:8 ccr 2 2 xorc #xx:8, ccr b ccr #xx:8 ccr 2 2 nop ? pc pc+2 2 ?????? 2 eepmov ? if r4l 04 ?????? (4) repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l ? 1 r4l until r4l=0 else next; notes: (1) set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) the number of states required for execution is 4n + 9 in the h8/3827r group and 4n + 8 in the h8/3827s group, h8/38327 group and h8/38427 group (n = value of r4l). (5) set to 1 if the divisor is negative; otherwise cleared to 0. (6) set to 1 if the divisor is zero; otherwise cleared to 0. #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code o perand s ize ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 513 of 626 rej09b0144-0600 a.2 operation code map table a.2 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 514 of 626 rej09b0144-0600 table a.2 operation code map high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * note: bit-manipulation instructions the push and pop instructions are identical in machine language to mov instructions. * appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 515 of 626 rej09b0144-0600 a.3 number of execution states the tables here can be used to calculate the number of states required for instruction execution. table a.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table a.3 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chip rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8 table a.3 number of cycles in each instruction access location execution status (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2? branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m ? internal operation s n 1 note: * depends on which on-chip module is accessed. see section 2.9.1, notes on data access for details. appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 516 of 626 rej09b0144-0600 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch a ddr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1, rd 1 adds.w #2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 517 of 626 rej09b0144-0600 instruction mnemonic instruction fetch i branch a ddr. read j stack operation k byte data access l word data access m internal operation n bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 bset rn, @aa:8 2 2 bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 518 of 626 rej09b0144-0600 instruction mnemonic instruction fetch i branch a ddr. read j stack operation k byte data access l word data access m internal operation n btst btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp. b #xx:8, rd 1 cmp. b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2 * 1 1 * 2 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16, rs), rd 2 1 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 2 1 mov.b rs, @?rd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 2 1 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 appendix a cpu instruction set rev. 6.00 aug 04, 2006 page 519 of 626 rej09b0144-0600 instruction mnemonic instruction fetch i branch a ddr. read j stack operation k byte data access l word data access m internal operation n mov mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 2 1 mov.w rs, @?rd 1 1 2 mov.w rs, @aa:16 2 1 mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1, rd 1 subs.w #2, rd 1 pop pop rd 1 1 2 push push rs 1 1 2 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 notes: 1. n: initial value in r4l. the source and destination operands are accessed n + 1 times each. 2. 1 in the h8/3827r group and 0 in the h8/3827s group, h8/38327 group, and h8/38427 group. appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 520 of 626 rej09b0144-0600 appendix b internal i/o registers b.1 addresses upper address: h'f0 bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'20 flmcr1 ? swe esu psu ev pv e p rom h'21flmcr2fler??????? h'22flpwcrpdwnd??????? h'23 ebr eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'24 h'25 h'26 h'27 h'28 h'29 h'2a h'2bfenrflshe??????? h'2c h'2d h'2e h'2f appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 521 of 626 rej09b0144-0600 upper address: h'ff bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'90 wegr wkegs7 wkegs6 wkegs5 wkegs4 wkegs3 wkegs2 wkegs1 wkegs0 system control h'91 spcr ? ? spc32 spc31 scinv3 scinv2 scinv1 scinv0 sci h'92cwosr???????cwostimer a h'93 h'94 h'95 eccsr ovh ovl ? ch2 cueh cuel crch crcl h'96 ech ech7 ech6 ech5 ech4 ech3 ech2 ech1 ech0 h'97 ecl ecl7 ecl6 ecl5 ecl4 ecl3 ecl2 ecl1 ecl0 asynchro- nous event counter h'98 smr31 com31 chr31 pe31 pm31 stop31 mp31 cks311 cks310 sci31 h'99 brr31 brr317 brr316 brr315 brr314 brr313 brr312 brr311 brr310 h'9a scr31 tie31 rie31 te31 re31 mpie31 teie31 cke31 cke310 h'9b tdr31 tdr317 tdr316 tdr315 tdr314 tdr313 tdr312 tdr311 tdr310 h'9c ssr31 tdre31 rdrf31 oer31 fer31 per31 tend31 mpbr31 mpbt31 h'9d rdr31 rdr317 rdr316 rdr315 rdr314 rdr313 rdr312 rdr311 rdr310 h'9e h'9f h'a0 h'a1 h'a2 h'a3 h'a4 h'a5 h'a6 h'a7 h'a8 smr32 com32 chr32 pe32 pm32 stop32 mp32 cks321 cks320 sci32 h'a9 brr32 brr327 brr326 brr325 brr324 br323 brr322 brr321 brr320 h'aa scr32 tie32 rie32 te32 re32 mpie32 teie32 cke321 cke320 h'ab tdr32 tdr327 tdr326 tdr325 tdr324 tdr323 tdr322 tdr321 tdr320 h'ac ssr32 tdre32 rdrf32 oer32 fer32 per32 tend32 mpbr32 mpbt32 h'ad rdr32 rdr327 rdr326 rdr325 rdr324 rdr323 rdr322 rdr321 rdr320 h'ae h'af h'b0 tma tma7 tma6 tma5 ? tma3 tma2 tma1 tma0 timer a appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 522 of 626 rej09b0144-0600 upper address: h'ff bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'b1 tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 timer a h'b2 tcsrw b6wi tcwe b4wi tcsrwe b2wi wdon bow1 wrst watchdog h'b3 tcw tcw7 tcw6 tcw5 tcw4 tcw3 tcw2 tcw1 tcwo timer h'b4 tmc tmc7 tmc6 tmc5 ? ? tmc2 tmc1 tmc0 timer c h'b5 tcc/tlc tcc/ tlc7 tcc6/ tlc6 tcc5/ tlc5 tcc4/ tlc4 tcc3/ tlc3 tcc2/ tlc2 tcc1/ tlc1 tcc0/ tlc0 h'b6 tcrf tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 timer f h'b7 tcsrf ovfh cmfh ovieh cclrh ovfl cmfl oviel cclrl h'b8 tcfh tcfh7 tcfh6 tcfh5 tcfh4 tcfh3 tcfh2 tcfh1 tcfh0 h'b9 tcfl tcfl7 tcfl6 tcfl5 tcfl4 tcfl3 tcfl2 tcfl1 tcfl0 h'ba ocrfh ocrfh7 ocrfh6 ocrfh5 ocrfh4 ocrfh3 ocrfh2 ocrfh1 ocrfh0 h'bb ocrfl ocrfl7 ocrfl6 ocrfl5 ocrfl4 ocrfl3 ocrfl2 ocrfl1 ocrfl0 h'bc tmg ovfh ovfl ovie iiegs cclr1 cclr0 cks1 cks0 timer g h'bd icrgf icrgf7 icrgf6 icrgf5 icrgf4 icrgf3 icrgf2 icrgf1 icrgfo h'be icrgr icrgr7 icrgr6 icrgr5 icrgr4 icrgr3 icrgr2 icrgr1 icrgro h'bf h'c0 lpcr dts1 dts0 cmx sgx sgs3 sgs2 sgs1 sgs0 lcd h'c1 lcr ? psw act disp cks3 cks2 cks1 cks0 controller/ h'c2 lcr2 lcdab ? ? ? cds3 cds2 cds1 cds0 driver h'c3 h'c4 adrrh adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 a/d h'c5 adrrl adr1 adr0 ??????converter h'c6 amr cks trge ? ? ch3 ch2 ch1 ch0 h'c7adsradsf??????? h'c8 pmr1 irq3 irq2 irq1 irq4 tmig tmofh tmofl tmow i/o port h'c9pmr2excl??????? h'ca pmr3 aevl aevh wdcks ncs irq0 reso ud pwm h'cb h'cc pmr5 wkp7 wkp6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 h'cd h'ce h'cf h'd0pwcr??????pwcr1pwcr0bit 14 h'd1 pwdru ? ? pwdru5 pwdru4 pwdru3 pwdru2 pwdru1 pwdru0 pwm h'd2 pwdrl pwdrl7 pwdrl6 pwdrl5 pwdrl4 pwdrl3 pwdrl2 pwdrl1 pwdrl0 h'd3 h'd4 pdr1 p17 p16 p15 p14 p13 p12 p11 p10 i/o port appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 523 of 626 rej09b0144-0600 upper address: h'ff bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'd5 i/o port h'd6 pdr3 p37 p36 p35 p34 p33 p32 p31 p30 h'd7pdr4????p43p42p41p40 h'd8 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 h'd9 pdr6 p67 p66 p65 p64 p63 p62 p61 p60 h'da pdr7 p77 p76 p75 p74 p73 p72 p71 p70 h'db pdr8 p87 p86 p85 p84 p83 p82 p81 p80 h'dc h'ddpdra????pa3pa2pa1pa0 h'de pdrb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'df h'e0 pucr1 pucr17 pucr16 pucr15 pucr14 pucr13 pucr12 pucr11 pucr10 i/o port h'e1 pucr3 pucr37 pucr36 pucr35 pucr34 pucr33 pucr32 pucr31 pucr30 h'e2 pucr5 pucr57 pucr56 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 h'e3 pucr6 pucr67 pucr66 pucr65 pucr64 pucr63 pucr62 pucr61 pucr60 h'e4 pcr1 pcr17 pcr16 pcr15 pcr14 pcr13 pcr12 pcr11 pcr10 h'e5 h'e6 pcr3 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 pcr30 h'e7pcr4?????pcr42pcr41pcr40 h'e8 pcr5 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 h'e9 pcr6 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 h'ea pcr7 pcr77 pcr76 pcr75 pcr74 pcr73 pcr72 pcr71 pcr70 h'eb pcr8 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 h'ec h'edpcra????pcra3pcra2pcra1pcra0 h'ee h'ef h'f0 syscr1 ssby sts2 sts1 sts0 lson ? ma1 ma0 system h'f1syscr2???n esel dton mson sa1 sa0 control h'f2iegr???ieg4ieg3ieg2ieg1ieg0 h'f3 ienr1 ienta ? ienwp ien4 ien3 ien2 ien1 ien0 h'f4 ienr2 iendt ienad ? ientg ientfh ientfl ientc ienec h'f5 h'f6 irr1 irrta ? ? irri4 irri3 irri2 irri1 irri0 h'f7 irri2 irrdt irrad ? irrtg irrtfh irrtfl irrtc irrec h'f8 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 524 of 626 rej09b0144-0600 upper address: h'ff bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'f9 iwpr iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 system h'fa ckstpr1 ? s31ckst p s32ckst p adckstp tgckstp tfckstp tcckstp tackstp control h'fbckstpr2???? aeckstp wdckst p pwckstp ldckstp h'fc h'fd h'fe h'ff legend: sci: serial communication interface appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 525 of 626 rej09b0144-0600 b.2 functions tmc?timer mode register c h'b4 timer c register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes (?) indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 ? 1 ? 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 ? 1 ? clock select 0 internal clock: internal clock: 0 0 1 internal clock: internal clock: 10 1 1 00 1 10 1 internal clock: internal clock: internal clock: external event (tmic): /8192 /2048 /512 /64 /16 /4 /4 rising or falling edge w counter up/down control tcc is an up-counter tcc is a down-counter 0 0 1 tcc up/down control is determined by input at pin ud. tcc is a down-counter if the ud input is high, and an up-counter if the ud input is low. 1 * auto-reload function select interval timer function selected * : don?t care auto-reload function selected 0 1 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 526 of 626 rej09b0144-0600 flmcr1?flash memory control register 1 h'f020 flash memory bit initial value read/write 7 ? 0 ? 6 swe 0 r/w 5 esu 0 r/w 0 p 0 r/w 2 pv 0 r/w 1 e 0 r/w 4 psu 0 r/w program 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when swe = 1 and psu = 1 erase 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when swe = 1 and esu = 1 program-verify 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when swe = 1 erase-verify 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when swe = 1 program-setup 0 program-setup cleared (initial value) 1 program setup [setting condition] when swe = 1 erase-setup 0 erase-setup cleared (initial value) 1 erase setup [setting condition] when swe = 1 software write enable bit 0 writing/erasing disabled (initial value) 1 writing/erasing enabled 3 ev 0 r/w appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 527 of 626 rej09b0144-0600 flmcr2?flash memory control register 2 h'f021 flash memory bit initial value read/write note: a write to flmcr2 is prohibited. 7 fler 0 r 6 ? 0 ? 5 ? 0 ? 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? 4 ? 0 ? flash memory error 3 ? 0 ? flpwcr?flash memory power control register h'f022 flash memory bit initial value read/write 7 pdwnd 0 r/w 6 ? 0 ? 5 ? 0 ? 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? 4 ? 0 ? power-down disable 0 when the system transits to sub-active mode, the flash memory changes to low-power mode 1 when the system transits to sub-active mode, the flash memory changes to normal mode 3 ? 0 ? appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 528 of 626 rej09b0144-0600 ebr?erase block register h'f023 flash memory bit initial value read/write note: set the bit of ebr to h'00 when erasing. 7 eb7 0 r/w 6 eb6 0 r/w 5 eb5 0 r/w 0 eb0 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w 4 eb4 0 r/w blocks 7 to 0 0 when a block of eb7 to eb0 is not selected (initial value) 1 when a block of eb7 to eb0 is selected 3 eb3 0 r/w fenr flash memory enable register h'f02b flash memory bit initial value read/write 7 flshe 0 r/w 6 ? 0 ? 5 ? 0 ? 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? 4 ? 0 ? flash memory control register enable 0 the flash memory control register cannot be accessed 1 the flash memory control register can be accessed 3 ? 0 ? appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 529 of 626 rej09b0144-0600 wegr?wakeup edge select register h'90 system control bit initial value read/write 7 wkegs7 0 r/w 6 wkegs6 0 r/w 5 wkegs5 0 r/w 0 wkegs0 0 r/w 2 wkegs2 0 r/w 1 wkegs1 0 r/w 4 wkegs4 0 r/w wkpn edge selected 0 wkpn pin falling edge detected (n = 0 to 7) 1 wkpn pin rising edge detected 3 wkegs3 0 r/w appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 530 of 626 rej09b0144-0600 spcr?serial port control register h'91 sci bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 spc32 0 r/w 0 scinv0 0 r/w 2 scinv2 0 r/w 1 scinv1 0 r/w 4 spc31 0 r/w rxd 31 pin input data inversion switch 0 rxd 31 input data is not inverted 1 rxd 31 input data is inverted txd 31 pin output data inversion switch 0 txd 31 output data is not inverted 1 txd 31 output data is inverted rxd 32 pin input data inversion switch 0 rxd 32 input data is not inverted 1 rxd 32 input data is inverted txd 32 pin output data inversion switch 0 txd 32 output data is not inverted 1 txd 32 output data is inverted p3 5 txd 31 pin function switch 0 functions as p3 5 i/o pin 1 functions as txd 31 output pin p4 2 /txd 32 pin function switch 0 function as p4 2 i/o pin 1 function as txd 32 output pin 3 scinv3 0 r/w appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 531 of 626 rej09b0144-0600 cwosr?subclock output select register h'92 timer a bit initial value read/write 7 ? 1 r 6 ? 1 r 5 ? 1 r 0 cwos 0 r/w 2 ? 1 r 1 ? 1 r 4 ? 1 r tmow pin clock select 0 clock output from tma is output 1 w is output 3 ? 1 r appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 532 of 626 rej09b0144-0600 eccsr?event counter control/status register h'95 aec bit initial value read/write note: * only a write of 0 for flag clearing is possible. 7 ovh 0 r/(w) * 6 ovl 0 r/(w) * 5 ? 0 r/w 0 crcl 0 r/w 2 cuel 0 r/w 1 crch 0 r/w 4 ch2 0 r/w counter reset control l 0 1 ecl is reset ecl reset is cleared and count-up function is enabled counter reset control h 0 ech is reset 1 ech reset is cleared and count-up function is enabled count-up enable l 0 ecl event clock input is disabled. ecl value is held 1 ecl event clock input is enabled count-up enable h 0 ech event clock input is disabled. ech value is held 1 ech event clock input is enabled channel select 0 ech and ecl are used together as a single- channel 16-bit event counter 1 ech and ecl are used as two independent 8-bit event counter channels counter overflow l 0 ecl has not overflowed 1 ecl has overflowed counter overflow h 0 ech has not overflowed 1 ech has overflowed 3 cueh 0 r/w appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 533 of 626 rej09b0144-0600 ech?event counter h h'96 aec bit initial value read/write 7 ech7 0 r 6 ech6 0 r 5 ech5 0 r 0 ech0 0 r 2 ech2 0 r 1 ech1 0 r 4 ech4 0 r count value 3 ech3 0 r note: ech and ecl can also be used as the upper and lower halves, respectively, of a 16-bit event counter (ec). ecl?event counter l h'97 aec bit initial value read/write 7 ecl7 0 r 6 ecl6 0 r 5 ecl5 0 r 0 ecl0 0 r 2 ecl2 0 r 1 ecl1 0 r 4 ecl4 0 r 3 ecl3 0 r count value note: ech and ecl can also be used as the upper and lower halves, respectively, of a 16-bit event counter (ec). appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 534 of 626 rej09b0144-0600 smr31?serial mode register 31 h'98 sci31 bit initial value read/write 7 com31 0 r/w 6 chr31 0 r/w 5 pe31 0 r/w 0 cks310 0 r/w 2 mp31 0 r/w 1 cks311 0 r/w 4 pm31 0 r/w clock select 0 0 01 1 1 1 clock w/2 clock 0 /16 clock /64 clock multiprocessor mode 0 multiprocessor communication function disabled 1 multiprocessor communication function enabled stop bit length 0 1 stop bit 1 2 stop bits parity mode 0 even parity 1 odd parity parity enable 0 parity bit addition and checking disabled 1 parity bit addition and checking enabled character length 0 8-bit data/5-bit data 1 7-bit data/5-bit data communication mode 0 asynchronous mode 1 synchronous mode 3 stop31 0 r/w appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 535 of 626 rej09b0144-0600 brr31?bit rate register31 h'99 sci31 bit initial value read/write 7 brr317 1 r/w 6 brr316 1 r/w 5 brr315 1 r/w 4 brr314 1 r/w 3 brr313 1 r/w 0 brr310 1 r/w 2 brr312 1 r/w 1 brr311 1 r/w serial transmit/receive bit rate appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 536 of 626 rej09b0144-0600 scr31?serial control register 31 h'9a sci31 bit initial value read/write 7 tie31 0 r/w 6 rie31 0 r/w 5 te31 0 r/w 0 cke310 0 r/w 2 teie31 0 r/w 1 cke311 0 r/w 4 re31 0 r/w receive interrupt enable 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled multiprocessor interrupt enable 0 multiprocessor interrupt request disabled (normal receive operation) [clearing condition] when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled the receive interrupt request (rxi), receive error interrupt request (eri), and setting of the rdrf, fer, and oer flags in the serial status register (ssr), are disabled until data with the multiprocessor bit set to 1 is received. transmit enable 0 transmit operation disabled (txd pin is transmit data pin) 1 transmit operation enabled (txd pin is transmit data pin) receive enable 0 receive operation disabled (rxd pin is i/o port) 1 receive operation enabled (rxd pin is receive data pin) transmit end interrupt enable clock enable 0 bit 1 cke311 0 0 1 1 bit 0 cke310 0 1 0 1 communication mode asynchronous synchronous asynchronous synchronous asynchronous synchronous asynchronous synchronous internal clock internal clock internal clock reserved (do not specify this combination) external clock external clock reserved (do not specify this combination) reserved (do not specify this combination) i/o port serial clock output clock output clock input serial clock input clock source sck pin function description transmit end interrupt request (tei) disabled 1 transmit end interrupt request (tei) enabled transmit interrupt enable 0 transmit data empty interrupt request (txi) disabled 1 transmit data empty interrupt request (txi) enabled 3 mpie31 0 r/w 3 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 537 of 626 rej09b0144-0600 tdr31?transmit data register 31 h'9b sci31 bit initial value read/write 7 tdr317 1 r/w 6 tdr316 1 r/w 5 tdr315 1 r/w 4 tdr314 1 r/w 3 tdr313 1 r/w 0 tdr310 1 r/w 2 tdr312 1 r/w 1 tdr311 1 r/w data for transfer to tsr appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 538 of 626 rej09b0144-0600 ssr31?serial status register31 h'9c sci3 bit initial value read/write note: * only a write of 0 for flag clearing is possible. 7 tdre31 1 r/(w) 6 rdrf31 0 r/(w) 5 oer31 0 r/(w) 0 mpbt31 0 r/w 2 tend31 1 r 1 mpbr31 0 r 4 fer31 0 r/(w) receive data register full 0 there is no receive data in rdr31 [clearing conditions] after reading rdrf31 = 1, cleared by writing 0 to rdrf31 when rdr31 data is read by an instruction 1 there is receive data in rdr31 [setting condition] when reception ends normally and receive data is transferred from rsr31 to rdr31 transmit data register empty 0 transmit data written in tdr31 has not been transferred to tsr31 [clearing conditions] after reading tdre31 = 1, cleared by writing 0 to tdre31 when data is written to tdr31 by an instruction 1 transmit data has not been written to tdr31, or transmit data written in tdr31 has been transferred to tsr31 [setting conditions] when bit te in serial control register 31 (scr31) is cleared to 0 when data is transferred from tdr31 to tsr31 transmit end 0 transmission in progress [clearing conditions] 1 transmission ended [setting conditions] parity error 0 reception in progress or completed normally [clearing condition] after reading per31 = 1, cleared by writing 0 to per31 1 a parity error has occurred during reception [setting condition] framing error 0 reception in progress or completed normally [clearing condition] after reading fer31 = 1, cleared by writing 0 to fer31 1 a framing error has occurred during reception [setting condition] when the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 overrun error 0 reception in progress or completed [clearing condition] after reading oer31 = 1, cleared by writing 0 to oer31 1 an overrun error has occurred during reception [setting condition] when the next serial reception is completed with rdrf31 set to 1 multiprocessor bit receive multiprocessor bit transfer 0 data in which the multiprocessor bit is 0 has been received 1 data in which the multiprocessor bit is 1 has been received 0 a 0 multiprocessor bit is transmitted 1 a 1 multiprocessor bit is transmitted 3 per31 0 r/(w) ***** after reading tdre31 = 1, cleared by writing 0 to tdre when data is written to tdr31 by an instruction when bit te in serial control register 31 (scr31) is cleared to 0 when bit tdre31 is set to 1 when the last bit of a transmit character is sent when the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (pm31) in the serial mode register (smr31) appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 539 of 626 rej09b0144-0600 rdr31?receive data register 31 h'9d sci31 bit initial value read/write 7 rdr317 0 r 6 rdr316 0 r 5 rdr315 0 r 4 rdr314 0 r 3 rdr313 0 r 0 rdr310 0 r 2 rdr312 0 r 1 rdr311 0 r serial receiving data are stored appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 540 of 626 rej09b0144-0600 smr32?serial mode register 32 h'a8 sci32 bit initial value read/write 7 com32 0 r/w 6 chr32 0 r/w 5 pe32 0 r/w 0 cks320 0 r/w 2 mp32 0 r/w 1 cks321 0 r/w 4 pm32 0 r/w clock select 0 0 01 1 1 1 clock w/2 clock 0 /16 clock /64 clock multiprocessor mode 0 multiprocessor communication function disabled 1 multiprocessor communication function enabled stop bit length 0 1 stop bit 1 2 stop bits parity mode 0 even parity 1 odd parity parity enable 0 parity bit addition and checking disabled 1 parity bit addition and checking enabled character length 0 8-bit data/5-bit data 1 7-bit data/5-bit data communication mode 0 asynchronous mode 1 synchronous mode 3 stop32 0 r/w appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 541 of 626 rej09b0144-0600 brr32?bit rate register 32 h'a9 sci32 bit initial value read/write 7 brr327 1 r/w 6 brr326 1 r/w 5 brr325 1 r/w 4 brr324 1 r/w 3 brr323 1 r/w 0 brr3120 1 r/w 2 brr322 1 r/w 1 brr321 1 r/w serial transmit/receive bit rate appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 542 of 626 rej09b0144-0600 scr32?serial control register 32 h'aa sci32 bit initial value read/write 7 tie32 0 r/w 6 rie32 0 r/w 5 te32 0 r/w 0 cke320 0 r/w 2 teie32 0 r/w 1 cke321 0 r/w 4 re32 0 r/w receive interrupt enable 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled multiprocessor interrupt enable 0 multiprocessor interrupt request disabled (normal receive operation) [clearing condition] when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled the receive interrupt request (rxi), receive error interrupt request (eri), and setting of the rdrf, fer, and oer flags in the serial status register (ssr), are disabled until data with the multiprocessor bit set to 1 is received. transmit enable 0 transmit operation disabled (txd pin is transmit data pin) 1 transmit operation enabled (txd pin is transmit data pin) receive enable 0 receive operation disabled (rxd pin is i/o port) 1 receive operation enabled (rxd pin is receive data pin) transmit end interrupt enable clock enable 0 bit 1 cke321 0 0 1 1 bit 0 cke320 0 1 0 1 communication mode asynchronous synchronous asynchronous synchronous asynchronous synchronous asynchronous synchronous internal clock internal clock internal clock reserved (do not specify this combination) external clock external clock reserved (do not specify this combination) reserved (do not specify this combination) i/o port serial clock output clock output clock input serial clock input clock source sck pin function description transmit end interrupt request (tei) disabled 1 transmit end interrupt request (tei) enabled transmit interrupt enable 0 transmit data empty interrupt request (txi) disabled 1 transmit data empty interrupt request (txi) enabled 3 mpie32 0 r/w 3 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 543 of 626 rej09b0144-0600 tdr32?transmit data register 32 h'ab sci32 bit initial value read/write 7 tdr327 1 r/w 6 tdr326 1 r/w 5 tdr325 1 r/w 4 tdr324 1 r/w 3 tdr323 1 r/w 0 tdr320 1 r/w 2 tdr322 1 r/w 1 tdr321 1 r/w data for transfer to tsr appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 544 of 626 rej09b0144-0600 ssr32?serial status register 32 h'ac sci32 bit initial value read/write note: * only a write of 0 for flag clearing is possible. 7 tdre32 1 r/(w) 6 rdrf32 0 r/(w) 5 oer32 0 r/(w) 0 mpbt32 0 r/w 2 tend32 1 r 1 mpbr32 0 r 4 fer32 0 r/(w) receive data register full 0 there is no receive data in rdr32 [clearing conditions] after reading rdrf32 = 1, cleared by writing 0 to rdrf32 when rdr32 data is read by an instruction 1 there is receive data in rdr32 [setting condition] when reception ends normally and receive data is transferred from rsr32 to rdr32 transmit data register empty 0 transmit data written in tdr32 has not been transferred to tsr32 [clearing conditions] after reading tdre32 = 1, cleared by writing 0 to tdre32 when data is written to tdr32 by an instruction 1 transmit data has not been written to tdr32, or transmit data written in tdr32 has been transferred to tsr32 [setting conditions] when bit te32 in serial control register 32 (scr32) is cleared to 0 when data is transferred from tdr32 to tsr32 transmit end 0 transmission in progress [clearing conditions] 1 transmission ended [setting conditions] parity error 0 reception in progress or completed normally [clearing condition] after reading per32 = 1, cleared by writing 0 to per32 1 a parity error has occurred during reception [setting condition] framing error 0 reception in progress or completed normally [clearing condition] after reading fer32 = 1, cleared by writing 0 to fer32 1 a framing error has occurred during reception [setting condition] when the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 overrun error 0 reception in progress or completed [clearing condition] after reading oer32 = 1, cleared by writing 0 to oer32 1 an overrun error has occurred during reception [setting condition] when the next serial reception is completed with rdrf32 set to 1 multiprocessor bit receive multiprocessor bit transfer 0 data in which the multiprocessor bit is 0 has been received 1 data in which the multiprocessor bit is 1 has been received 0 a 0 multiprocessor bit is transmitted 1 a 1 multiprocessor bit is transmitted 3 per32 0 r/(w) ***** after reading tdre32 = 1, cleared by writing 0 to tdre32 when data is written to tdr32 by an instruction when bit te in serial control register 32 (scr32) is cleared to 0 when bit tdre32 is set to 1 when the last bit of a transmit character is sent when the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (pm32) in the serial mode register (smr32) appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 545 of 626 rej09b0144-0600 rdr32?receive data register 32 h'ad sci32 bit initial value read/write 7 rdr327 0 r 6 rdr326 0 r 5 rdr325 0 r 4 rdr324 0 r 3 rdr323 0 r 0 rdr320 0 r 2 rdr322 0 r 1 rdr321 0 r serial receiving data are stored appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 546 of 626 rej09b0144-0600 tma?timer mode register a h'b0 timer a bit initial value read/write 7 tma7 0 r/w 6 tma6 0 r/w 5 tma5 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w internal clock select tma3 tma2 0 pss pss pss pss 0 4 ? 1 ? clock output select * 0 note: * values when the cwos bit in cwosr is cleared to 0. when the cwos bit is set to 1, w is output regardless of the value of bits tma7 to tma5. /32 /16 tma1 0 1 tma0 0 0 1 1 pss pss pss pss 10 1 0 0 1 1 1 psw psw psw psw 00 1 0 0 1 1 psw and tca are reset 10 1 0 0 1 1 prescaler and divider ratio or overflow period /8192 /4096 /2048 /512 /256 /128 /32 /8 1 s 0.5 s 0.25 s 0.03125 s interval timer time base (when using 32.768 khz) function 0 0 1 /8 /4 10 1 1 00 1 10 1 /32 w /16 w /8 w /4 w 3 tma3 0 r/w appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 547 of 626 rej09b0144-0600 tca?timer counter a h'b1 timer a bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r count value appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 548 of 626 rej09b0144-0600 tcsrw?timer control/status register w h'b2 watchdog timer bit initial value read/write 7 b6wi 1 r 6 tcwe 0 r/(w) 5 b4wi 1 r 4 tcsrwe 0 r/(w) 3 b2wi 1 r 0 wrst 0 r/(w) 2 wdon 0 r/(w) 1 b0wi 1 r ** * * watchdog timer reset 0 [clearing conditions] 1 [setting condition] when tcw overflows and a reset signal is generated reset by res pin when tcsrwe = 1, and 0 is written in both b0wi and wrst bit 0 write inhibit 0 bit 0 is write-enabled bit 0 is write-protected 1 watchdog timer on 0 watchdog timer operation is disabled watchdog timer operation is enabled 1 bit 2 write inhibit 0 bit 2 is write-enabled bit 2 is write-protected 1 timer control/status register w write enable 0 data cannot be written to bits 2 and 0 data can be written to bits 2 and 0 1 bit 4 write inhibit 0 bit 4 is write-enabled bit 4 is write-protected 1 timer counter w write enable 0 data cannot be written to tcw data can be written to tcw 1 bit 6 write inhibit 0 bit 6 is write-enabled bit 6 is write-protected 1 note: * write is permitted only under certain conditions. appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 549 of 626 rej09b0144-0600 tcw?timer counter w h'b3 watchdog timer bit initial value read/write 7 tcw7 0 r/w 6 tcw6 0 r/w 5 tcw5 0 r/w 4 tcw4 0 r/w 3 tcw3 0 r/w 0 tcw0 0 r/w 2 tcw2 0 r/w 1 tcw1 0 r/w count value tmc?timer mode register c h'b4 timer c bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 ? 1 ? 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 ? 1 ? auto-reload function select clock select internal clock: internal clock: 0 1 internal clock: internal clock: 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 internal clock: internal clock: internal clock: external event (tmic): counting on rising or falling edge * : don ? t care /8192 /2048 /512 /64 /16 /4 w /4 0 interval timer function selected 1 auto-reload function selected counter up/down control 0 tcc is an up-counter 1 tcc is a down-counter * hardware control of tcc up/down operation by ud pin input ud pin input high: down-counter ud pin input low: up-counter 0 0 1 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 550 of 626 rej09b0144-0600 tcc?timer counter c h'b5 timer c bit initial value read/write note: tcc is assigned to the same address as tlc. in a read, the tcc value is read. 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r count value tlc?timer load register c h'b5 timer c bit initial value read/write note: tlc is assigned to the same address as tcc. in a write, the tlc value is written. 7 tlc7 0 r/w 6 tlc6 0 r/w 5 tlc5 0 r/w 4 tlc4 0 r/w 3 tlc3 0 r/w 0 tlc0 0 r/w 2 tlc2 0 r/w 1 tlc1 0 r/w reload value appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 551 of 626 rej09b0144-0600 tcrf?timer control register f h'b6 timer f bit initial value read/write 7 tolh 0 w 6 cksh2 0 w 5 cksh1 0 w 0 cksl0 0 w 2 cksl2 0 w 1 cksl1 0 w 4 cksh0 0 w clock select l 0 counting on external event (tmif) rising/falling edge internal clock /32 internal clock /16 internal clock /4 internal clock w/4 1 1 1 1 * 0 0 1 1 * 0 1 0 1 toggle output level l 0 low level 1 high level toggle output level h 0 low level 1 high level 3 toll 0 w clock select h 0 overflow signal internal clock /32 internal clock /16 internal clock /4 internal clock w/4 16-bit mode, counting on tcfl * : don ? t care 1 1 1 1 * 0 0 1 1 * 0 1 0 1 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 552 of 626 rej09b0144-0600 tcsrf?timer control/status register f h'b7 timer f bit initial value read/write note: * bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. 7 ovfh 0 r/(w) 6 cmfh 0 r/(w) 5 ovieh 0 r/w 0 cclrl 0 r/w 2 cmfl 0 r/(w) 1 oviel 0 r/w 4 cclrh 0 r/w compare match flag h 0 [clearing condition] after reading cmfh = 1, cleared by writing 0 to cmfh 1 [setting condition] set when the tcfh value matches the ocrfh value timer overflow flag h 0 [clearing condition] after reading ovfh = 1, cleared by writing 0 to ovfh 1 [setting condition] set when tcfh overflows from h'ff to h'00 compare match flag l 0 [clearing condition] after reading cmfl = 1, cleared by writing 0 to cmfl 1 [setting condition] set when the tcfl value matches the ocrfl value timer overflow flag l 0 [clearing condition] after reading ovfl = 1, cleared by writing 0 to ovfl 1 [setting condition] set when tcfl overflows from h'ff to h'00 counter clear h 0 16-bit mode: tcf clearing by compare match is disabled 8-bit mode: tcfh clearing by compare match is disabled 1 16-bit mode: tcf clearing by compare match is enabled 8-bit mode: tcfh clearing by compare match is enabled timer overflow interrupt enable h 0 tcfh overflow interrupt request is disabled 1 tcfh overflow interrupt request is enabled timer overflow interrupt enable l counter clear l 0 tcfl overflow interrupt request is disabled 1 tcfl overflow interrupt request is enabled 0 tcfl clearing by compare match is disabled 1 tcfl clearing by compare match is enabled 3 ovfl 0 r/(w) ** ** appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 553 of 626 rej09b0144-0600 tcfh?8-bit timer counter fh h'b8 timer f bit initial value read/write 7 tcfh7 0 r/w 6 tcfh6 0 r/w 5 tcfh5 0 r/w 4 tcfh4 0 r/w 3 tcfh3 0 r/w 0 tcfh0 0 r/w 2 tcfh2 0 r/w 1 tcfh1 0 r/w count value note: tcfh and tcfl can also be used as the upper and lower halves, respectively, of a 16-bit event counter (tcf). tcfl?8-bit timer counter fl h'b9 timer f bit initial value read/write 7 tcfl7 0 r/w 6 tcfl6 0 r/w 5 tcfl5 0 r/w 4 tcfl4 0 r/w 3 tcfl3 0 r/w 0 tcfl0 0 r/w 2 tcfl2 0 r/w 1 tcfl1 0 r/w count value note: tcfh and tcfl can also be used as the upper and lower halves, respectively, of a 16-bit event counter (tcf). appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 554 of 626 rej09b0144-0600 ocrfh?output compare register fh h'ba timer f bit initial value read/write 7 ocrfh7 1 r/w 6 ocrfh6 1 r/w 5 ocrfh5 1 r/w 4 ocrfh4 1 r/w 3 ocrfh3 1 r/w 0 ocrfh0 1 r/w 2 ocrfh2 1 r/w 1 ocrfh1 1 r/w note: ech and ecl can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (ocrf). ocrfl?output compare register fl h'bb timer f bit initial value read/write 7 ocrfl7 1 r/w 6 ocrfl6 1 r/w 5 ocrfl5 1 r/w 4 ocrfl4 1 r/w 3 ocrfl3 1 r/w 0 ocrfl0 1 r/w 2 ocrfl2 1 r/w 1 ocrfl1 1 r/w note: ech and ecl can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (ocrf). appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 555 of 626 rej09b0144-0600 tmg?timer mode register g h'bc timer g bit initial value read/write 7 ovfh 0 r/(w) * 6 ovfl 0 r/(w) * 5 ovie 0 w 3 cclr1 0 w 0 cks0 0 w 2 cclr0 0 w 1 cks1 0 w 4 iiegs 0 w timer overflow flag h counter clear tcg clearing is disabled tcg cleared by falling edge of input capture input signal tcg cleared by rising edge of input capture input signal tcg cleared by both edges of input capture input signal 0 1 0 1 0 0 1 1 timer overflow interrupt enable tcg overflow interrupt request is disabled tcg overflow interrupt request is enabled 0 1 0 [clearing condition] after reading ovfh = 1, cleared by writing 0 to ovfh 1 [setting condition] set when tcg overflows from h'ff to h'00 note: * bits 7 and 6 can only be written with 0, for flag clearing. timer overflow flag l 0 [clearing condition] after reading ovfl = 1, cleared by writing 0 to ovfl 1 [setting condition] set when tcg overflows from h'ff to h'00 input capture interrupt edge select 0 interrupt generated on rising edge of input capture input signal 1 interrupt generated on falling edge of input capture input signal clock select 0 internal clock: counting on /64 0 internal clock: counting on /32 0 1 1 internal clock: counting on /2 1 internal clock: counting on w/4 0 1 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 556 of 626 rej09b0144-0600 icrgf?input capture register gf h'bd timer g bit initial value read/write 7 icrgf7 0 r 6 icrgf6 0 r 5 icrgf5 0 r 4 icrgf4 0 r 3 icrgf3 0 r 0 icrgf0 0 r 2 icrgf2 0 r 1 icrgf1 0 r stores tcg value at falling edge of input capture signal icrgr?input capture register gr h'be timer g bit initial value read/write 7 icrgr7 0 r 6 icrgr6 0 r 5 icrgr5 0 r 4 icrgr4 0 r 3 icrgr3 0 r 0 icrgr0 0 r 2 icrgr2 0 r 1 icrgr1 0 r stores tcg value at rising edge of input capture signal appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 557 of 626 rej09b0144-0600 lpcr?lcd port control register h'c0 lcd controller/driver bit initial value read/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w 4 sgx 0 r/w clock enable bit 3 sgs3 0 0 0 0 0 1 0 * bit 4 sgx 0 1 bit 2 sgs2 0 0 0 1 1 * 0 * bit 1 sgs1 0 0 1 0 1 * 0 * bit 0 sgs0 0 1 * * * * 0 * function of pins seg 32 to seg 1 3 sgs3 0 r/w bit 4 sgx 0 pins seg 32 to seg 29 * (initial value) 1 pins cl 1 , cl 2 , do, m description port port seg seg seg seg port * seg 32 to seg 29 port port seg seg seg seg port seg 28 to seg 25 port port port seg seg seg port seg 24 to seg 21 port port port seg seg seg port use prohibited note: * seg32 to seg29 are external expansion pins. note: * these pins function as ports when the setting of sgs3 to sgs0 is 0000 or 0001. in the case of the h8/38327 group and h8/38427 group the initial values of these bits must not be changed. seg 20 to seg 17 port port port port seg seg port seg 16 to seg 13 port port port port seg seg port seg 12 to seg 9 port port port port port seg port seg 8 to seg 5 port port port port port seg port notes (initial value) seg 4 to seg 1 duty select, common function select bit 7 dts1 0 0 1 1 bit 6 dts0 0 1 0 1 bit 5 cmx 0 1 0 1 0 1 0 1 duty cycle static 1/2 duty 1/3 duty 1/4 duty common drivers com 1 com 4 to com 1 com 2 to com 1 com 4 to com 1 com 3 to com 1 com 4 to com 1 com 4 to com 1 com 4 to com 2 output the same waveform as com 1 com 4 outputs the same waveform as com 3 and com 2 outputs the same waveform as com 1 com 4 outputs a non-selected waveform notes ? * : don't care appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 558 of 626 rej09b0144-0600 lcr?lcd control register h'c1 lcd controller/driver bit initial value read/write 7 ? 1 ? 6 psw 0 r/w 5 act 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 4 disp 0 r/w lcd drive power supply on/off control frame frequency select operating clock bit 1 bit 2 bit 3 0 0 0 1 1 1 1 1 1 1 1 * * * 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 * 0 1 0 1 0 1 0 1 bit 0 cks1 cks2 cks3 cks0 w w /2 w /4 /2 /4 /8 /16 /32 /64 /128 /256 display function activate lcd controller/driver operation halted lcd controller/driver operates : don ? t care * 0 1 0 lcd drive power supply off 1 lcd drive power supply on display data control 0 blank data is displayed 1 lcd ram data is displayed appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 559 of 626 rej09b0144-0600 lcr2?lcd control register 2 h'c2 lcd bit initial value read/write 7 lcdab 0 r/w 6 ? 1 ? 5 ? 1 ? 3 cds3 0 r/w 0 cds0 0 r/w 2 cds2 0 r/w 1 cds1 0 r/w 4 ? 0 r/w a waveform/b waveform switching control charge/discharge pulse duty cycle select duty cycle bit 1 bit 2 bit 3 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 * * 0 1 0 1 0 1 0 1 * * 1 1/8 2/8 3/8 4/8 5/8 6/8 0 1/16 1/32 bit 0 cds1 cds2 cds3 cds0 : don ? t care * 0 drive using a waveform 1 drive using b waveform appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 560 of 626 rej09b0144-0600 adrrh?a/d result register h h'c4 a/d converter adrrl?a/d result register l h'c5 bit initial value read/write adrrh 7 adr9 not fixed r 6 adr8 not fixed r 5 adr7 not fixed r 3 adr5 not fixed r 0 adr2 not fixed r 2 adr4 not fixed r 1 adr3 not fixed r 4 adr6 not fixed r a/d conversion result bit initial value read/write adrrl 7 adr1 not fixed r 6 adr0 not fixed r 5 ? ? ? 3 ? ? ? 0 ? ? ? 2 ? ? ? 1 ? ? ? 4 ? ? ? a/d conversion result appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 561 of 626 rej09b0144-0600 amr?a/d mode register h'c6 a/d converter bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 4 ? 1 ? 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w channel select no channel selected bit 3 0 bit 2 analog input channel * : don ? t care ch3 ch2 0 ch1 ch0 bit 1 bit 0 0an 1 1 0 1 1 00 1 1 * external trigger select 0 disables start of a/d conversion by external trigger 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg 5 ? 1 ? 4 an 5 an 6 an 7 * setting prohibited ** 100 1 10 1 an 0 an 1 an 2 an 3 clock select 62/ bit 7 0 conversion period cks 31/ 1 62 s = 1 mhz 31 s 12.4 s = 5 mhz ? conversion time appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 562 of 626 rej09b0144-0600 adsr?a/d start register h'c7 a/d converter bit initial value read/write 7 adsf 0 r/w 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? a/d status flag 0 1 read write read write indicates completion of a/d conversion stops a/d conversion indicates a/d conversion in progress starts a/d conversion appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 563 of 626 rej09b0144-0600 pmr1?port mode register 1 h'c8 i/o port bit initial value read/write 7 irq3 0 r/w 6 irq2 0 r/w 5 irq1 0 r/w 3 tmig 0 r/w 0 tmow 0 r/w 2 tmofh 0 r/w 1 tmofl 0 r/w 4 irq4 0 r/w p1 0 /tmow pin function switch 0 functions as p1 0 i/o pin 1 functions as tmow output pin p1 2 /tmofh pin function switch 0 functions as p1 2 i/o pin 1 functions as tmofh output pin p1 3 /tmig pin function switch 0 functions as p1 3 i/o pin 1 functions as tmig input pin p1 4 /irq 4 /adtrg pin function switch 0 functions as p1 4 i/o pin 1 functions as irq 4 / adtrg input pin p1 5 /irq 1 /tmic pin function switch 0 functions as p1 5 i/o pin 1 functions as irq 1 /tmic input pin p1 1 /tmofl pin function switch 0 functions as p1 1 i/o pin 1 functions as tmofl output pin p1 6 /irq 2 pin function switch 0 functions as p1 6 i/o pin 1 functions as irq 2 input pin p1 7 /irq 3 /tmif pin function switch 0 functions as p1 7 i/o pin 1 functions as irq 3 /tmif input pin appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 564 of 626 rej09b0144-0600 pmr2?port mode register 2 h'c9 i/o port bit initial value read/write 7 excl 0 r/w 6 ? 1 r 5 ? 0 r/w 4 ? 1 r 3 ? 1 r 0 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w p3 1 /ud/excl pin function switch 0 1 functions as p3 1 /ud i/o pin functions as excl input pin note: the information on this register applies to the h8/38327 group and h8/38427 group. appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 565 of 626 rej09b0144-0600 pmr3?port mode register 3 h'ca i/o port bit initial value read/write note: * in the h8/38327 group and h8/38427 group this bit is reserved and cannot be written to. 7 aevl 0 r/w 6 aevh 0 r/w 5 wdcks 0 r/w 3 irq0 0 r/w 0 pwm 0 r/w 2 reso * 0 r/w 1 ud 0 r/w 4 ncs 0 r/w p3 0 /pwm pin function switch 0 functions as p3 0 i/o pin 1 functions as pwm output pin p3 2 /reso pin function switch 0 functions as p3 2 i/o pin 1 functions as reso i/o pin p4 3 /irq 0 pin function switch 0 functions as p4 3 i/o pin 1 functions as irq 0 input pin watchdog timer switch 0 8192 1 p3 1 /ud pin function switch 0 functions as p3 1 i/o pin 1 functions as ud input pin tmig noise canceler select 0 noise cancellation function not used 1 noise cancellation function used p3 6 /aevh pin function switch 0 functions as p3 6 i/o pin functions as aevh input pin w /4 1 p3 7 /aevl pin function switch 0 functions as p3 7 i/o pin 1 functions as aevl input pin appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 566 of 626 rej09b0144-0600 pmr5?port mode register 5 h'cc i/o port bit initial value read/write 7 wkp 7 0 r/w 6 wkp 6 0 r/w 5 wkp 5 0 r/w 3 wkp 3 0 r/w 0 wkp 0 0 r/w 2 wkp 2 0 r/w 1 wkp 1 0 r/w 4 wkp 4 0 r/w p5 n /wkp n /seg n +1 pin function switch 0 functions as p5 n i/o pin (n = 7 to 0) 1 functions as wkp n input pin pwcr?pwm control register h'd0 14-bit pwm bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 pwcr0 0 w 2 ? 1 ? 1 pwcr1 0 w clock select 0 the input clock is /2 (t * = 2/ ) the conversion period is 16,384/ , with a minimum modulation width of 1/ the input clock is /4 (t * = 4/ ) the conversion period is 32,768/ , with a minimum modulation width of 2/ 1 the input clock is /8 (t * = 8/ ) the conversion period is 65,536/ , with a minimum modulation width of 4/ the input clock is /16 (t * = 16/ ) the conversion period is 131,072/ , with a minimum modulation width of 8/ note: * t : period of pwm input clock appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 567 of 626 rej09b0144-0600 pwdru?pwm data register u h'd1 14-bit pwm bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w upper 6 bits of data for generating pwm waveform pwdru5 pwdru4pwdru3 pwdru0 pwdru2 pwdur1 pwdrl?pwm data register l h'd2 14-bit pwm bit initial value read/write 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w lower 8 bits of data for generating pwm waveform pwdrl5 pwdrl4 pwdrl3 pwdrl0 pwdrl2 pwdrl1 pwdrl6 pwdrl7 pdr1?port data register 1 h'd4 i/o ports bit initial value read/write 7 p1 0 r/w 6 p1 0 r/w 5 p1 0 r/w 4 p1 0 r/w 3 p1 0 r/w 0 p1 0 r/w 2 p1 0 r/w 1 p1 0 r/w 7 6543210 data for port 1 pins pdr3?port data register 3 h'd6 i/o ports bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 r/w 2 p3 0 r/w 1 p3 0 r/w 0 2 3 4 5 6 7 1 data for port 3 pins appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 568 of 626 rej09b0144-0600 pdr4?port data register 4 h'd7 i/o ports bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 p4 1 r 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 30 21 data for port pins p4 2 to p4 0 pin p4 3 state is read pdr5?port data register 5 h'd8 i/o ports bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 30 21 4 5 6 7 data for port 5 pins pdr6?port data register 6 h'd9 i/o ports bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 30 21 4 5 6 7 data for port 6 pins pdr7?port data register 7 h'da i/o ports bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 3210 4 5 6 7 data for port 7 pins appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 569 of 626 rej09b0144-0600 pdr8?port data register 8 h'db i/o ports bit initial value read/write 7 p8 0 r/w 6 p8 0 r/w 5 p8 0 r/w 4 p8 0 r/w 3 p8 0 r/w 0 p8 0 r/w 2 p8 0 r/w 1 p8 0 r/w 30 21 4 5 6 7 data for port 8 pins pdra?port data register a h'dd i/o ports bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 30 21 data for port a pins pdrb?port data register b h'de i/o ports bit read/write 7 pb r 6 pb r 5 pb r 4 pb r 3 pb r 0 pb r 2 pb r 1 pb r 30 21 4 5 6 7 data for port b pins appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 570 of 626 rej09b0144-0600 pucr1?port pull-up control register 1 h'e0 i/o ports bit initial value read/write 7 pucr1 0 r/w 6 pucr1 0 r/w 5 pucr1 0 r/w 4 pucr1 0 r/w 3 pucr1 0 r/w 0 pucr1 0 r/w 2 pucr1 0 r/w 1 pucr1 0 r/w 0 43 21 5 6 7 0 1 input pull-up mos is off input pull-up mos is on port 1 input pull-up mos control note: when the pcr1 specification is 0. (input port specification) pucr3?port pull-up control register 3 h'e1 i/o ports bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 0 2 3 4 5 6 7 1 0 1 input pull-up mos is off input pull-up mos is on port 3 input pull-up mos control note: when the pcr3 specification is 0. (input port specification) pucr5?port pull-up control register 5 h'e2 i/o ports bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 30 21 4 5 6 7 0 1 input pull-up mos is off input pull-up mos is on port 5 input pull-up mos control note: when the pcr5 specification is 0. (input port specification) appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 571 of 626 rej09b0144-0600 pucr6?port pull-up control register 6 h'e3 i/o ports bit initial value read/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 30 21 4 5 6 7 0 1 input pull-up mos is off input pull-up mos is on port 6 input pull-up mos control note: when the pcr6 specification is 0. (input port specification) pcr1?port control register 1 h'e4 i/o ports bit initial value read/write 7 pcr1 0 w 6 pcr1 0 w 5 pcr1 0 w 4 pcr1 0 w 3 pcr1 0 w 0 pcr1 0 w 2 pcr1 0 w 1 pcr1 0 w port 1 input/output select 0 input pin 1 output pin 7 6543210 pcr3?port control register 3 h'e6 i/o ports bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 w 2 pcr3 0 w 1 pcr3 0 w port 3 input/output select 0 input pin 1 output pin 0 2 3 4 5 6 7 1 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 572 of 626 rej09b0144-0600 pcr4?port control register 4 h'e7 i/o ports bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w port 4 input/output select 0 input pin 1 output pin 0 21 pcr5?port control register 5 h'e8 i/o ports bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w port 5 input/output select 0 input pin 1 output pin 76543 0 21 pcr6?port control register 6 h'e9 i/o ports bit initial value read/write 7 pcr6 0 w 6 pcr6 0 w 5 pcr6 0 w 4 pcr6 0 w 3 pcr6 0 w 0 pcr6 0 w 2 pcr6 0 w 1 pcr6 0 w port 6 input/output select 0 input pin 1 output pin 76543 0 21 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 573 of 626 rej09b0144-0600 pcr7?port control register 7 h'ea i/o ports bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w port 7 input/output select 0 input pin 1 output pin 76543210 pcr8?port control register 8 h'eb i/o ports bit initial value read/write 7 pcr8 0 w 6 pcr8 0 w 5 pcr8 0 w 4 pcr8 0 w 3 pcr8 0 w 0 pcr8 0 w 2 pcr8 0 w 1 pcr8 0 w port 8 input/output select 0 input pin 1 output pin 76543 0 21 pcra?port control register a h'ed i/o ports bit initial value read/write 7 ? 0 ? 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 pcra 0 w 0 pcra 0 w 2 pcra 0 w 1 pcra 0 w 0 1 2 3 port a input/output select 0 input pin 1 output pin appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 574 of 626 rej09b0144-0600 syscr1?system control register 1 h'f0 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 3 lson 0 r/w 0 ma0 1 r/w 2 ? 1 ? 1 ma1 1 r/w 4 sts0 0 r/w software standby 0 when a sleep instruction is executed in active mode, a transition is made to sleep mode 1 standby timer select 2 to 0 0 wait time = 8,192 states wait time = 16,384 states 0 0 1 wait time = 32,768 states wait time = 65,536 states 10 1 active (medium-speed) mode clock select /16 /32 0 1 0 0 1 1 /64 /128 1 1 00 10 1 wait time = 131,072 states wait time = 2 states wait time = 8 states wait time = 16 states low speed on flag 0 the cpu operates on the system clock ( ) 1 the cpu operates on the subclock ( ) sub when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode when a sleep instruction is executed in subactive mode, a transition is made to watch mode osc osc osc osc appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 575 of 626 rej09b0144-0600 syscr2?system control register 2 h'f1 system control bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w 4 nesel 1 r/w subactive mode clock select 0 /8 /4 0 1 1 /2 * w w w direct transfer on flag 0 when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode 1 when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1 medium speed on flag 0 operates in active (high-speed) mode 1 operates in active (medium-speed) mode noise elimination sampling frequency select 0 sampling rate is /16 1 sampling rate is /4 osc osc * : don ? t care appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 576 of 626 rej09b0144-0600 iegr?irq edge select register h'f2 system control bit initial value read/write 7 ? 0 ? 6 ? 1 ? 4 ieg4 0 r/w 3 ieg3 0 r/w 0 ieg0 0 r/w 2 ieg2 0 r/w 1 ieg1 0 r/w 5 ? 1 ? irq 0 edge select 0 falling edge of irq 0 pin input is detected rising edge of irq 0 pin input is detected 1 irq 1 edge select 0 falling edge of irq 1 , tmic pin input is detected rising edge of irq 1 , tmic pin input is detected 1 irq 2 edge select 0 falling edge of irq 2 pin input is detected rising edge of irq 2 pin input is detected 1 irq 3 edge select 0 falling edge of irq 3 , tmif pin input is detected rising edge of irq 3 , tmif pin input is detected 1 irq 4 edge select 0 falling edge of irq 4 pin and adtrg pin is detected rising edge of irq 4 pin and adtrg pin is detected 1 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 577 of 626 rej09b0144-0600 ienr1?interrupt enable register 1 h'f3 system control bit initial value read/write 7 ienta 0 r/w 6 ? 0 r/w 4 ien4 0 r/w 3 ien3 0 r/w 0 ien0 0 r/w 2 ien2 0 r/w 1 ien1 0 r/w 5 ienwp 0 r/w irq 4 to irq 0 interrupt enable 0 disables irq 4 to irq 0 interrupt requests enables irq 4 to irq 0 interrupt requests 1 wakeup interrupt enable 0 disables wkp 7 to wkp 0 interrupt requests enables wkp 7 to wkp 0 interrupt requests 1 timer a interrupt enable 0 disables timer a interrupt requests enables timer a interrupt requests 1 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 578 of 626 rej09b0144-0600 ienr2?interrupt enable register 2 h'f4 system control bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 ? 0 r/w 3 ientfh 0 r/w 0 ienec 0 r/w 2 ientfl 0 r/w 1 ientc 0 r/w 4 ientg 0 r/w asynchronous event counter interrupt enable 0 disables asynchronous event counter interrupt requests 1 enables asynchronous event counter interrupt requests timer fl interrupt enable 0 disables timer fl interrupt requests 1 enables timer fl interrupt requests timer fh interrupt enable 0 disables timer fh interrupt requests 1 enables timer fh interrupt requests timer g interrupt enable 0 disables timer g interrupt requests 1 enables timer g interrupt requests a/d converter interrupt enable 0 disables a/d converter interrupt requests 1 enables a/d converter interrupt requests timer c interrupt enable 0 disables timer c interrupt requests 1 enables timer c interrupt requests direct transition interrupt enable 0 disables direct transition interrupt requests 1 enables direct transition interrupt requests appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 579 of 626 rej09b0144-0600 irr1?interrupt request register 1 h'f6 system control bit initial value read/write 7 irrta 0 r/(w) * 6 ? 0 r/(w) * 5 ? 1 ? 3 irri3 0 r/(w) * 0 irri0 0 r/(w) * 2 irri2 0 r/(w) * 1 irri1 0 r/(w) * 4 irri4 0 r/(w) * irq4 to irq0 interrupt request flags 0 [clearing condition] when irrin = 1, it is cleared by writing 0 (n = 4 to 0) note: * bits 7 and 4 to 0 can only be written with 0, for flag clearing. 1 [setting condition] when pin irq n is designated for interrupt input and the designated signal edge is input timer a interrupt request flag 0 [clearing condition] when irrta = 1, it is cleared by writing 0 1 [setting condition] when the timer a counter value overflows (from h'ff to h'00) appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 580 of 626 rej09b0144-0600 irr2?interrupt request register 2 h'f7 system control bit initial value read/write 7 irrdt 0 r/(w) * 6 irrad 0 r/(w) * 5 ? 0 r/w 3 irrtfh 0 r/(w) * 0 irrec 0 r/(w) * 2 irrtfl 0 r/(w) * 1 irrtc 0 r/(w) * 4 irrtg 0 r/(w) * timer g interrupt request flag timer c interrupt request flag 0 [clearing condition] when irrtg = 1, it is cleared by writing 0 1 [setting condition] when the tmig pin is designated for tmig input and the designated signal edge is input note: * bits 7, 6 and 4 to 0 can only be written with 0, for flag clearing. a/d converter interrupt request flag 0 [clearing condition] when irrad = 1, it is cleared by writing 0 1 [setting condition] when the a/d converter completes conversion and adsf is reset direct transition interrupt request flag 0 [clearing condition] when irrdt = 1, it is cleared by writing 0 1 [setting condition] when a sleep instruction is executed while dton is set to 1, and a direct transition is made timer fh interrupt request flag 0 [clearing condition] when irrtfh = 1, it is cleared by writing 0 1 [setting condition] when counter fh and output compare register fh match in 8-bit timer mode, or when 16-bit counters fl and fh and output compare registers fl and fh match in 16-bit timer mode timer fl interrupt request flag 0 [clearing condition] when irrtfl = 1, it is cleared by writing 0 1 [setting condition] when counter fl and output compare register fl match in 8-bit timer mode asynchronous event counter interrupt request flag 0 [clearing condition] when irrec = 1, it is cleared by writing 0 1 [setting condition] when the asynchronous event counter value overflows 0 [clearing condition] when irrtc = 1, it is cleared by writing 0 1 [setting condition] when the timer c counter value overflows (from h'ff to h'00) or underflows (from h'00 to h'ff) appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 581 of 626 rej09b0144-0600 iwpr?wakeup interrupt request register h'f9 system control bit initial value read/write 7 iwpf7 0 r/(w) * 6 iwpf6 0 r/(w) * 5 iwpf5 0 r/(w) * 3 iwpf3 0 r/(w) * 0 iwpf0 0 r/(w) * 2 iwpf2 0 r/(w) * 1 iwpf1 0 r/(w) * 4 iwpf4 0 r/(w) * 0 [clearing condition] when iwpfn = 1, it is cleared by writing 0 (n = 7 to 0) note: * all bits can only be written with 0, for flag clearing. wakeup interrupt request register 1 [setting condition] when pin wkp n is designated for wakeup input and a falling edge is input at that pin appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 582 of 626 rej09b0144-0600 ckstpr1?clock stop register 1 h'fa system control bit initial value read/write 7 ? 1 r/w 6 s31ckstp 1 r/w 5 s32ckstp 1 r/w 3 tgckstp 1 r/w 0 tackstp 1 r/w 2 tfckstp 1 r/w 1 tcckstp 1 r/w 4 adckstp 1 r/w timer a module standby mode control timer f module standby mode control 0 timer f is set to module standby mode timer f module standby mode is cleared 1 timer g interrupt enable 0 timer g is set to module standby mode timer g module standby mode is cleared 1 a/d converter module standby mode control 0 a/d converter is set to module standby mode a/d converter module standby mode is cleared 1 timer c module standby mode control 0 timer c is set to module standby mode timer c module standby mode is cleared 1 0 timer a is set to module standby mode timer a module standby mode is cleared 1 sci3-2 module standby mode control 0 sci3-2 is set to module standby mode sci3-2 module standby mode is cleared 1 sci3-1 module standby mode control 0 sci3-1 is set to module standby mode sci3-1 module standby mode is cleared 1 appendix b internal i/o registers rev. 6.00 aug 04, 2006 page 583 of 626 rej09b0144-0600 ckstpr2?clock stop register 2 h'fb system control bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 3 aeckstp 1 r/w 0 ldckstp 1 r/w 2 wdckstp 1 r/w 1 pwckstp 1 r/w 4 ? 1 ? lcd module standby mode control wdt module standby mode control 0 wdt is set to module standby mode wdt module standby mode is cleared 1 asynchronous event counter module standby mode control 0 asynchronous event counter is set to module standby mode asynchronous event counter module standby mode is cleared 1 pwm module standby mode control 0 pwm is set to module standby mode pwm module standby mode is cleared 1 0 lcd is set to module standby mode lcd module standby mode is cleared 1 appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 584 of 626 rej09b0144-0600 appendix c i/o port block diagrams c.1 block diagrams of port 1 v cc v cc v ss pucr1 n pmr1 n pdr1 n pcr1 n irq n?4/n * sby (low level during reset and in standby mode) internal data bus pdr1: pcr1: pmr1: pucr1: * : n = 7 to 5 n ? 4 n = 4 n port data register 1 port control register 1 port mode register 1 port pull-up control register 1 p1 n figure c.1 (a) port 1 block diagram (pins p1 7 to p1 4 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 585 of 626 rej09b0144-0600 v cc v cc sby v ss pucr1 3 pmr1 3 pdr1 3 pcr1 3 timer g module tmig internal data bus p1 3 figure c.1 (b) port 1 block diagram (pin p1 3 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 586 of 626 rej09b0144-0600 v cc v cc v ss pucr1 n pmr1 n pdr1 n pcr1 n sby internal data bus pdr1: pcr1: pmr1: pucr1: n= 2, 1 port data register 1 port control register 1 port mode register 1 port pull-up control register 1 tmofh (p1 2 ) tmofl (p1 1 ) timer f module p1 n figure c.1 (c) port 1 block diagram (pin p1 2 , p1 1 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 587 of 626 rej09b0144-0600 v cc v cc v ss pucr1 0 pmr1 0 pdr1 0 pcr1 0 sby internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 tmow timer a module p1 0 figure c.1 (d) port 1 block diagram (pin p1 0 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 588 of 626 rej09b0144-0600 c.2 block diagrams of port 3 p3 n v cc v cc pucr3 n pmr3 n pdr3 n pcr3 n aec module internal data bus sby v ss aevh(p3 6 ) aevl(p3 7 ) pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 n=7 to 6 figure c.2 (a) port 3 block diagram (pin p3 7 to p3 6 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 589 of 626 rej09b0144-0600 p3 5 sci31 module pdr3 5 pucr3 5 scinv1 spc31 pcr3 5 sby v ss pdr3: port data register 3 pcr3: port control register 3 pucr3: port pull-up control register 3 scinv1: bit 1 of serial port control register (spcr) spc31: bit 4 of serial port control register (spcr) txd31 internal data bus v cc v cc figure c.2 (b) port 3 block diagram (pin p3 5 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 590 of 626 rej09b0144-0600 p3 4 v cc v cc sci31 module pdr3 4 pcr3 4 scinv0 sby v ss pdr3: port data register 3 pcr3: port control register 3 pucr3: port pull-up control register 3 scinv0: bit 0 of serial port control register (spcr) re31 rxd31 internal data bus pucr3 4 figure c.2 (c) port 3 block diagram (pin p3 4 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 591 of 626 rej09b0144-0600 p3 3 v cc sci31 module pdr3 3 pcr3 3 sby v ss pdr3: port data register 3 pcr3: port control register 3 pucr3: port pull-up control register 3 sckie31 sckoe31 scko31 scki31 internal data bus pucr3 3 v cc figure c.2 (d) port 3 block diagram (pin p3 3 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 592 of 626 rej09b0144-0600 p3 2 v cc v cc pucr3 2 internal data bus pmr3 2 pdr3 2 pcr3 2 sby v ss pdr3: port data register 3 pcr3: port control register 3 pmr3: port mode register 3 pucr3: port pull-up control register 3 reso figure c.2 (e-1) port 3 block diagram (pin p3 2 , h8/3827r group and h8/3827s group) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 593 of 626 rej09b0144-0600 p3 2 v cc v cc pucr3 2 internal data bus pmr3 2 pdr3 2 pcr3 2 sby v ss pdr3: port data register 3 pcr3: port control register 3 pmr3: port mode register 3 pucr3: port pull-up control register 3 figure c.2 (e-2) port 3 block diagram (pin p3 2 in the mask rom version of the h8/38327 group and h8/38427 group) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 594 of 626 rej09b0144-0600 p3 2 v cc v cc pucr3 2 internal data bus pmr3 2 pdr3 2 pcr3 2 sby v ss pdr3: port data register 3 pcr3: port control register 3 pmr3: port mode register 3 pucr3: port pull-up control register 3 reset signal (low level during reset) figure c.2 (e-3) port 3 block diagram (pin p3 2 in the f-ztat version of the h8/38327 group and h8/38427 group) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 595 of 626 rej09b0144-0600 v cc v cc v ss pucr3 1 pdr3 1 pcr3 1 ud sby internal data bus pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 p3 1 timer c module pmr3 1 figure c.2 (f-1) port 3 block diagram (pin p3 1 , h8/3827r group and h8/3827s group) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 596 of 626 rej09b0144-0600 v cc v cc v ss pucr3 1 pdr3 1 pcr3 1 ud pmr2 7 sby internal data bus pdr3: pcr3: pmr3: pmr2: pucr3: port data register 3 port control register 3 port mode register 3 port mode register 2 port p ull-u p control re g ister 3 p3 1 timer c module clock input subcloc k oscillator pmr3 1 figure c.2 (f-2) port 3 block diagram (pin p3 1 , h8/38327 group and h8/38427 group) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 597 of 626 rej09b0144-0600 p3 0 v cc v cc pucr3 0 pmr3 0 pdr3 0 pcr3 0 sby v ss pdr3: port data register 3 pcr3: port control register 3 pmr3: port mode register 3 pucr3: port pull-up control register 3 pwm pwm module internal data bus figure c.2 (g) port 3 block diagram (pin p3 0 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 598 of 626 rej09b0144-0600 c.3 block diagrams of port 4 p4 3 pmr3 3 internal data bus irq 0 pmr3: port mode register 3 figure c.3 (a) port 4 block diagram (pin p4 3 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 599 of 626 rej09b0144-0600 p4 2 sci32 module internal data bus pdr4 2 scinv3 pcr4 2 sby v ss pdr4: port data register 4 pcr4: port control register 4 scinv3: bit 3 of serial port control register (spcr) spc32: bit 5 of serial port control register (spcr) txd32 v cc spc32 figure c.3 (b) port 4 block diagram (pin p4 2 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 600 of 626 rej09b0144-0600 p4 1 v cc sci32 module pdr4 1 pcr4 1 sby v ss pdr4: port data register 4 pcr4: port control register 4 scinv2: bit 2 of serial port control register (spcr) re32 rxd32 internal data bus scinv2 figure c.3 (c) port 4 block diagram (pin p4 1 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 601 of 626 rej09b0144-0600 p4 0 v cc sci32 module pdr4 0 pcr4 0 sby v ss pdr4: port data register 4 pcr4: port control register 4 sckie32 sckoe32 scko32 internal data bus scki32 figure c.3 (d) port 4 block diagram (pin p4 0 ) appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 602 of 626 rej09b0144-0600 c.4 block diagram of port 5 p5 n v cc v cc pucr5 n internal data bus pmr5 n pdr5 n pcr5 n sby v ss wkp n pdr5: port data register 5 pcr5: port control register 5 pmr5: port mode register 5 pucr5: port pull-up control register 5 n = 7 to 0 figure c.4 port 5 block diagram appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 603 of 626 rej09b0144-0600 c.5 block diagram of port 6 p6 n v cc v cc pucr6 n pdr6 n internal data bus pcr6 n sby v ss pdr6: port data register 6 pcr6: port control register 6 pucr6: port pull-up control register 6 n = 7 to 0 figure c.5 port 6 block diagram appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 604 of 626 rej09b0144-0600 c.6 block diagram of port 7 p7 n v cc pdr7 n internal data bus pcr7 n sby v ss pdr7: port data register 7 pcr7: port control register 7 n = 7 to 0 figure c.6 port 7 block diagram appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 605 of 626 rej09b0144-0600 c.7 block diagrams of port 8 p8 n v cc pdr8 n internal data bus pcr8 n sby v ss pdr8: port data register 8 pcr8: port control register 8 n= 7 to 0 figure c.7 port 8 block diagram appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 606 of 626 rej09b0144-0600 c.8 block diagram of port a pa n v cc pdra n internal data bus pcra n sby v ss pdra: port data register a pcra: port control register a n = 3 to 0 figure c.8 port a block diagram appendix c i/o port block diagrams rev. 6.00 aug 04, 2006 page 607 of 626 rej09b0144-0600 c.9 block diagram of port b pb n internal data bus amr3 to amr0 a/d module v in n = 7 to 0 dec figure c.9 port b block diagram appendix d port states in the different processing states rev. 6.00 aug 04, 2006 page 608 of 626 rej09b0144-0400 appendix d port states in the different processing states table d.1 port states overview port reset sleep subsleep standby watch subactive active p1 7 to p1 0 high impedance retained retained high impedance * 1 retained functions functions p3 7 to p3 0 high impedance * 2 retained retained high impedance * 1 retained functions functions p4 3 to p4 0 high impedance retained retained high impedance retained functions functions p5 7 to p5 0 high impedance retained retained high impedance * 1 retained functions functions p6 7 to p6 0 high impedance retained retained high impedance retained functions functions p7 7 to p7 0 high impedance retained retained high impedance retained functions functions p8 7 to p8 0 high impedance retained retained high impedance retained functions functions pa 3 to pa 0 high impedance retained retained high impedance retained functions functions pb 7 to pb 0 high impedance high impedance high impedance high impedance high impedance high impedance high impedance notes: 1. high level output when mos pull-up is in on state. 2. reset output from p3 2 pin only (h8/3827r group and h8/3827s group). on-chip pull-up mos turns on for pin p3 2 only (f-ztat version of the h8/38327 group and h8/38427 group). appendix e list of product codes rev. 6.00 aug 04, 2006 page 609 of 626 rej09b0144-0600 appendix e list of product codes table e.1 h8/3827r group, h8/3827s group, and h8/38327 group product code lineup product type product code mark code package (package code) h8/3822r hd6433822rh hd6433822r( *** )h 80-pin qfp (fp-80a) h8/3827r group regular products hd6433822rf hd6433822r( *** )f 80-pin qfp (fp-80b) mask rom versions hd6433822rw hd6433822r( *** )w 80-pin tqfp (tfp-80c) hcd6433822r ? die hd6433822rd hd6433822r( *** )h 80-pin qfp (fp-80a) hd6433822re hd6433822r( *** )f 80-pin qfp (fp-80b) wide-range specification products hd6433822rwi hd6433822r( *** )w 80-pin tqfp (tfp-80c) h8/3823r hd6433823rh hd6433823r( *** )h 80-pin qfp (fp-80a) regular products hd6433823rf hd6433823r( *** )f 80-pin qfp (fp-80b) mask rom versions hd6433823rw hd6433823r( *** )w 80-pin tqfp (tfp-80c) hcd6433823r ? die hd6433823rd hd6433823r( *** )h 80-pin qfp (fp-80a) hd6433823re hd6433823r( *** )f 80-pin qfp (fp-80b) wide-range specification products hd6433823rwi hd6433823r( *** )w 80-pin tqfp (tfp-80c) h8/3824r hd6433824rh hd6433824r( *** )h 80-pin qfp (fp-80a) regular products hd6433824rf hd6433824r( *** )f 80-pin qfp (fp-80b) mask rom versions hd6433824rw hd6433824r( *** )w 80-pin tqfp (tfp-80c) hcd6433824r ? die hd6433824rd hd6433824r( *** )h 80-pin qfp (fp-80a) hd6433824re hd6433824r( *** )f 80-pin qfp (fp-80b) wide-range specification products hd6433824rwi hd6433824r( *** )w 80-pin tqfp (tfp-80c) h8/3825r hd6433825rh hd6433825r( *** )h 80-pin qfp (fp-80a) regular products hd6433825rf hd6433825r( *** )f 80-pin qfp (fp-80b) mask rom versions hd6433825rw hd6433825r( *** )w 80-pin tqfp (tfp-80c) hcd6433825r ? die hd6433825rd hd6433825r( *** )h 80-pin qfp (fp-80a) hd6433825re hd6433825r( *** )f 80-pin qfp (fp-80b) wide-range specification products hd6433825rwi hd6433825r( *** )w 80-pin tqfp (tfp-80c) appendix e list of product codes rev. 6.00 aug 04, 2006 page 610 of 626 rej09b0144-0400 product type product code mark code package (package code) h8/3826r hd6433826rh hd6433826r( *** )h 80-pin qfp (fp-80a) h8/3827r group regular products hd6433826rf hd6433826r( *** )f 80-pin qfp (fp-80b) mask rom versions hd6433826rw hd6433826r( *** )w 80-pin tqfp (tfp-80c) hcd6433826r ? die hd6433826rd hd6433826r( *** )h 80-pin qfp (fp-80a) hd6433826re hd6433826r( *** )f 80-pin qfp (fp-80b) wide-range specification products hd6433826rwi hd6433826r( *** )w 80-pin tqfp (tfp-80c) h8/3827r hd6433827rh hd6433827r( *** )h 80-pin qfp (fp-80a) regular products hd6433827rf hd6433827r( *** )f 80-pin qfp (fp-80b) mask rom versions hd6433827rw hd6433827r( *** )w 80-pin tqfp (tfp-80c) hcd6433827r ? die hd6433827rd hd6433827r( *** )h 80-pin qfp (fp-80a) hd6433827re hd6433827r( *** )f 80-pin qfp (fp-80b) wide-range specification products hd6433827rwi hd6433827r( *** )w 80-pin tqfp (tfp-80c) hd6473827rh hd6473827rh 80-pin qfp (fp-80a) ztat versions regular products hd6473827rf hd6473827rf 80-pin qfp (fp-80b) hd6473827rw hd6473827rw 80-pin tqfp (tfp-80c) hd6473827rd hd6473827rh 80-pin qfp (fp-80a) hd6473827re hd6473827rf 80-pin qfp (fp-80b) wide-range specification products hd6473827rwi hd6473827rw 80-pin tqfp (tfp-80c) h8/3824s HD6433824Sh HD6433824S( *** )h 80-pin qfp (fp-80a) h8/3827s group HD6433824Sw HD6433824S( *** )w 80-pin tqfp (tfp-80c) regular products hcd6433824s ? die mask rom versions HD6433824Sd HD6433824S( *** )h 80-pin qfp (fp-80a) wide-range specification products HD6433824Swi HD6433824S( *** )w 80-pin tqfp (tfp-80c) h8/3825s hd6433825sh hd6433825s( *** )h 80-pin qfp (fp-80a) hd6433825sw hd6433825s( *** )w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd6433825s ? die hd6433825sd hd6433825s( *** )h 80-pin qfp (fp-80a) wide-range specification products hd6433825swi hd6433825s( *** )w 80-pin tqfp (tfp-80c) appendix e list of product codes rev. 6.00 aug 04, 2006 page 611 of 626 rej09b0144-0600 product type product code mark code package (package code) hd6433826sh hd6433826s( *** )h 80-pin qfp (fp-80a) hd6433826sw hd6433826s( *** )w 80-pin tqfp (tfp-80c) h8/3827s group h8/3826s mask rom versions regular products hcd6433826s ? die hd6433826sd hd6433826s( *** )h 80-pin qfp (fp-80a) wide-range specification products hd6433826swi hd6433826s( *** )w 80-pin tqfp (tfp-80c) h8/3827s hd6433827sh hd6433827s( *** )h 80-pin qfp (fp-80a) hd6433827sw hd6433827s( *** )w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd6433827s ? die hd6433827sd hd6433827s( *** )h 80-pin qfp (fp-80a) wide-range specification products hd6433827swi hd6433827s( *** )w 80-pin tqfp (tfp-80c) h8/38322 hd64338322h 38322h 80-pin qfp (fp-80a) h8/38327 group hd64338322w 38322w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338322 ? die hd64338322hw 38322h 80-pin qfp (fp-80a) wide-range specification products hd64338322ww 38322w 80-pin tqfp (tfp-80c) h8/38323 hd64338323h 38323h 80-pin qfp (fp-80a) hd64338323w 38323w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338323 ? die hd64338323hw 38323h 80-pin qfp (fp-80a) wide-range specification products hd64338323ww 38323w 80-pin tqfp (tfp-80c) h8/38324 hd64338324h 38324h 80-pin qfp (fp-80a) hd64338324w 38324w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338324 ? die hd64338324hw 38324h 80-pin qfp (fp-80a) wide-range specification products hd64338324ww 38324w 80-pin tqfp (tfp-80c) hd64f38324h f38324h 80-pin qfp (fp-80a) f-ztat versions regular products hd64f38324w f38324w 80-pin tqfp (tfp-80c) hd64f38324hw f38324h 80-pin qfp (fp-80a) wide-range specification products hd64f38324ww f38324w 80-pin tqfp (tfp-80c) appendix e list of product codes rev. 6.00 aug 04, 2006 page 612 of 626 rej09b0144-0400 product type product code mark code package (package code) h8/38325 hd64338325h 38325h 80-pin qfp (fp-80a) h8/38327 group hd64338325w 38325w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338325 ? die hd64338325hw 38325h 80-pin qfp (fp-80a) wide-range specification products hd64338325ww 38325w 80-pin tqfp (tfp-80c) h8/38326 hd64338326h 38326h 80-pin qfp (fp-80a) hd64338326w 38326w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338326 ? die hd64338326hw 38326h 80-pin qfp (fp-80a) wide-range specification products hd64338326ww 38326w 80-pin tqfp (tfp-80c) h8/38327 hd64338327h 38327h 80-pin qfp (fp-80a) hd64338327w 38327w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338327 ? die hd64338327hw 38327h 80-pin qfp (fp-80a) wide-range specification products hd64338327ww 38327w 80-pin tqfp (tfp-80c) hd64f38327h f38327h 80-pin qfp (fp-80a) hd64f38327w f38327w 80-pin tqfp (tfp-80c) f-ztat versions regular products hcd64f38327 ? die hd64f38327hw f38327h 80-pin qfp (fp-80a) wide-range specification products hd64f38327ww f38327w 80-pin tqfp (tfp-80c) h8/38422 hd64338422h 38422h 80-pin qfp (fp-80a) h8/38427 group hd64338422w 38422w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338422 ? die hd64338422hw 38422h 80-pin qfp (fp-80a) wide-range specification products hd64338422ww 38422w 80-pin tqfp (tfp-80c) h8/38423 hd64338423h 38423h 80-pin qfp (fp-80a) hd64338423w 38423w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338423 ? die hd64338423hw 38423h 80-pin qfp (fp-80a) wide-range specification products hd64338423ww 38423w 80-pin tqfp (tfp-80c) appendix e list of product codes rev. 6.00 aug 04, 2006 page 613 of 626 rej09b0144-0600 product type product code mark code package (package code) h8/38424 hd64338424h 38424h 80-pin qfp (fp-80a) h8/38427 group hd64338424w 38424w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338424 ? die hd64338424hw 38424h 80-pin qfp (fp-80a) wide-range specification products hd64338424ww 38424w 80-pin tqfp (tfp-80c) hd64f38424h f38424h 80-pin qfp (fp-80a) f-ztat versions regular products hd64f38424w f38424w 80-pin tqfp (tfp-80c) hd64f38424hw f38424h 80-pin qfp (fp-80a) wide-range specification products hd64f38424ww f38424w 80-pin tqfp (tfp-80c) h8/38425 hd64338425h 38425h 80-pin qfp (fp-80a) hd64338425w 38425w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338425 ? die hd64338425hw 38425h 80-pin qfp (fp-80a) wide-range specification products hd64338425ww 38425w 80-pin tqfp (tfp-80c) h8/38426 hd64338426h 38426h 80-pin qfp (fp-80a) hd64338426w 38426w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338426 ? die hd64338426hw 38426h 80-pin qfp (fp-80a) wide-range specification products hd64338426ww 38426w 80-pin tqfp (tfp-80c) h8/38427 hd64338427h 38427h 80-pin qfp (fp-80a) hd64338427w 38427w 80-pin tqfp (tfp-80c) mask rom versions regular products hcd64338427 ? die hd64338427hw 38427h 80-pin qfp (fp-80a) wide-range specification products hd64338427ww 38427w 80-pin tqfp (tfp-80c) hd64f38427h f38427h 80-pin qfp (fp-80a) hd64f38427w f38427w 80-pin tqfp (tfp-80c) f-ztat versions regular products hcd64f38427 ? die hd64f38427hw f38427h 80-pin qfp (fp-80a) wide-range specification products hd64f38427ww f38427w 80-pin tqfp (tfp-80c) note: for mask rom versions, ( *** ) is the rom code. appendix f package dimensions rev. 6.00 aug 04, 2006 page 614 of 626 rej09b0144-0400 appendix f package dimensions dimensional drawings of h8/3827r group, h8/3827s group, h8/38327 group, and h8/38427 group packages fp-80a, fp-80b and tfp-80c are shown in figures f.1, f.2 (only h8/3827r group) and f.3 below. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. * 1 * 2 * 3 p e d e d 80 1 f 20 21 61 60 41 40 yxm z z e h d h b 2 1 1 detail f c a a l a l terminal cross section p 1 1 c b c b prqp0080jb-a p-qfp80-14x14-0.65 0.83 0.83 0.10 0.12 0.65 0 ? 8 ? 3.05 0.12 0.17 0.22 0.24 0.32 0.40 0.00 0.30 0.15 0.10 0.25 17.5 17.2 16.9 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e d a c e e l h 1.2g mass[typ.] 1.6 16.9 17.2 17.5 2.70 14 reference symbol dimension in millimeters min nom max 0.5 0.8 1.1 previous code jeita package code renesas code fp-80a/fp-80av 14 figure f.1 fp-80a package dimensions appendix f package dimensions rev. 6.00 aug 04, 2006 page 615 of 626 rej09b0144-0600 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. prqp0080gd-b p-qfp80-14x20-0.80 1.0 0.8 0.15 0.15 0.8 10 ? 0 ? 0.30 0.20 0.15 0.35 0.00 0.45 0.37 0.29 0.22 0.17 0.12 3.10 20 14 19.2 18.4 18.8 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e d a c e e l h 1.7g mass[typ.] fp-80b/fp-80bv renesas code jeita package code previous code 1.4 1.2 1.0 max nom min dimension in millimeters symbol reference 2.70 25.2 24.8 24.4 2.4 * 1 * 2 * 3 p e d e d 41 40 64 65 24 25 1 80 f ymx z z b h e h d 2 1 1 detail f c l aa a l terminal cross section p 1 1 b c b c figure f.2 fp-80b package dimensions appendix f package dimensions rev. 6.00 aug 04, 2006 page 616 of 626 rej09b0144-0400 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. ptqp0080kc-a p-tqfp80-12x12-0.50 12 tfp-80c/tfp-80cv renesas code jeita package code previous code 0.6 0.5 0.4 max nom min dimension in millimeters symbol reference 12 1.00 14.2 14.0 13.8 1.0 mass[typ.] 0.4g h l e e c a e a h a b b c x y z z l 2 d e 1 p 1 1 d e 1 d 13.8 14.0 14.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 ? 8 ? 0.5 0.10 0.10 1.25 1.25 index mark * 1 * 2 * 3 y f 80 1 m x 20 21 61 60 41 40 d e d e p b h e h d z z detail f 1 12 c l a a a l 1 1 p terminal cross section b c c b figure f.3 tfp-80c package dimensions appendix g specifications of chip form rev. 6.00 aug 04, 2006 page 617 of 626 rej09b0144-0600 appendix g specifications of chip form the specifications of the chip form of the hcd6433827r, hcd6433826r, hcd6433825r, hcd6433824r, hcd6433823r, and hcd6433822r are shown in figure g.1. x-direction y-direction 6.10 0.05 6.23 0.05 0.28 0.22 x-direction y-direction 6.10 0.25 6.23 0.25 maximum plain max 0.03 (unit: mm) figure g.1 chip sectional figure the specifications of the chip form of the hcd6433827s, hcd6433826s, hcd6433825s, and hcd6433824s are shown in figure g.2. x-direction y-direction 3.55 0.05 3.45 0.05 0.28 0.22 x-direction y-direction 3.55 0.25 3.45 0.25 max 0.03 (unit: mm) maximum plain figure g.2 chip sectional figure appendix g specifications of chip form rev. 6.00 aug 04, 2006 page 618 of 626 rej09b0144-0400 the specifications of the chip form of the hcd64f38327 and hcd64f38427 are shown in figure g.3. x-direction y-direction 4.35 0.05 4.83 0.05 0.28 0.22 x-direction y-direction 4.35 0.25 4.83 0.25 maximum plain pattern side chip back max 0.03 (unit: mm) figure g.3 chip sectional figure the specifications of the chip form of the h8/38327 group (mask rom version) and h8/38427 group (mask rom version) are shown in figure g.4. 0.28 0.22 x-direction y-direction 3.45 0.05 3.39 0.05 x-direction y-direction 3.45 0.25 3.39 0.25 maximum plain pattern side chip back max 0.03 (unit: mm) figure g.4 chip sectional figure appendix h form of bonding pads rev. 6.00 aug 04, 2006 page 619 of 626 rej09b0144-0600 appendix h form of bonding pads the form of the bonding pads for the hcd6433827r, hcd6433826r, hcd6433825r, hcd6433824r, hcd6433823r, and hcd6433822r is shown in figure h.1. 90 m 90 m 5 to 8 m 5 to 8 m bonding area metal layer figure h.1 bonding pad form appendix h form of bonding pads rev. 6.00 aug 04, 2006 page 620 of 626 rej09b0144-0400 the form of the bonding pads for the hcd6433827s, hcd6433826s, hcd6433825s, and hcd6433824s is shown in figure h.2. 75 m 75 m 2.5 m 2.5 m bonding area metal layer figure h.2 bonding pad form appendix h form of bonding pads rev. 6.00 aug 04, 2006 page 621 of 626 rej09b0144-0600 the form of the bonding pads for the hcd64f38327, hcd64f38427, h8/38327 group (mask rom version), and h8/38427 group (mask rom version) is shown in figure h.3. bonding area metal layer 65 m 65 m 5 m 5 m figure h.3 bonding pad form appendix i specifications of chip tray rev. 6.00 aug 04, 2006 page 622 of 626 rej09b0144-0400 appendix i specifications of chip tray the specifications of the chip tray for the hcd6433827r, hcd6433826r, hcd6433825r, hcd6433824r, hcd6433823r, and hcd6433822r is shown in figure i.1. 51 51 6.23 6.10 xx' 0.40.1 8.70.1 1.80.1 4.00.1 8.10.15 6.60.05 6.60.05 chip-tray code name manufactured by dainippon ink and chemicals, incorporated code name: ct054 characteristic engraving: tct066066-041 chip orientation chip type code 8.10.1 8.70.1 (unit: mm) cross-sectional view: x to x' figure i.1 specifications of chip tray appendix i specifications of chip tray rev. 6.00 aug 04, 2006 page 623 of 626 rej09b0144-0600 the specifications of the chip tray for the hcd6433827s, hcd6433826s, hcd6433825s, and hcd6433824s is shown in figure i.2. 51 51 3.45 3.55 xx' 0.60.1 4.90.1 5.90.1 1.80.1 4.00.1 5.90.1 4.00.05 4.00.05 chip-tray code name manufactured by dainippon ink and chemicals, incorporated code name: ct065 characteristic engraving: tct4040-060 chip orientation chip type code base type code 4.90.1 (unit: mm) cross-sectional view: x to x' figure i.2 specifications of chip tray appendix i specifications of chip tray rev. 6.00 aug 04, 2006 page 624 of 626 rej09b0144-0400 the specifications of the chip tray for the hcd64f38327 and hcd64f38427 is shown in figure i.3. type code chip orientation chip 4.83 4.35 chip-tray code name code name: ct037 characteristic engraving: 2ct049049-070 5.4 0.1 4.9 0.05 x' 6.6 0.1 1.8 0.1 4.0 0.1 5.4 0.1 6.6 0.1 (unit: mm) cross-sectional view: x to x' 0.7 0.1 x 4.9 0.05 51 51 figure i.3 specifications of chip tray appendix i specifications of chip tray rev. 6.00 aug 04, 2006 page 625 of 626 rej09b0144-0600 the specifications of the chip tray for the h8/38327 group (mask rom version) and h8/38427 group (mask rom version) is shown in figure i.4. type code chip orientation chip 3.39 3.45 chip-tray code name code name: ct022 characteristic engraving: tct036036-060 4.48 0.1 3.6 0.05 x' 5.34 0.1 1.8 0.1 4.0 0.1 4.48 0.1 5.34 0.1 (unit: mm) cross-sectional view: x to x' 0.6 0.1 x 3.6 0.05 51 51 figure i.4 specifications of chip tray appendix i specifications of chip tray rev. 6.00 aug 04, 2006 page 626 of 626 rej09b0144-0400 renesas 8-bit single-chip microcomputer hardware manual h8/3827r group, h8/3827s group, h8/38327 group, h8/38427 group publication date: 1st edition, september, 1999 rev.6.00, august 04, 2006 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ?2006. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0 h8/3827r group, h8/3827s group, h8/38327 group, h8/38427 group hardware manual |
Price & Availability of HD6433824S
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |